S-curve Engineering for ON-state Performance using Anti-ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

In this work, we report that the AFE/FE gate-stack can be utilized to engineer the S-curve for boosting the I_ON of NC-FinFET. By using a short-channel BSIM-CMG compatible AFE/FE stack NC-FinFET model, the capacitance matching and ON-state performance for AFE/FE stack NC-FinFETs are investigated. Our study indicates that, the AFE/FE gate-stack can be used to improve the capacitance matching in strong inversion at higher gate-bias. Therefore, impressively higher ON-state current (compared to single-layer) can be achieved. In reality, source-drain series resistance will make such high IDS impractical. The more likely strategy is to use lower V_DD to achieve much lower power consumption (and reduced vertical fields). While the transient NC effect also needs to be carefully investigated, this study suggests significant long term benefits to V_DD scaling if materials with certain AFE and FE properties are developed and introduced in IC manufacturing in the future.