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Simulation of Different Structured Gate-All-Around FETs at 3 nm Node for Low-Power Integrated Circuits

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posted on 2022-09-29, 03:11 authored by Nathan Totorica, Wei Hu, Feng LiFeng Li

 This paper compares different types of GAA FET structures at 3 nm technology node using TCAD simulation, including Lateral Nanosheet, Lateral Nanowire, Vertical Nanosheet, and Vertical Nanowire. Single gate and gate stack structures are included in the analysis. The performance is evaluated using the key device parameters such as on-state current, leakage-current, thresh-old voltage for transfer characteristics, drain-induced barrier lowering (DIBL) and subthreshold slope (SS) for short-channel effects. Among the four GAA structures we found that, under the same effective width, Lateral Nanowire structure shows the highest on-state current, but also the worst performance in short channel effects. In contrast, Vertical Nanosheet shows the lowest DIBL and SS, thanks to  


Micron Technology Foundation


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Submitting Author's Institution

University of Idaho

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  • United States of America