Temperature Dependent Characteristics and Electrostatic Threshold Voltage Tuning of Accumulated Body MOSFETs

Narrow-channel accumulated body nMOSFET devices with p-type side-gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing (Vside). The subthreshold slope (SS) and drain induced barrier lowering (DIBL) decrease and threshold voltage (Vt) increases linearly with reduced temperature and reduced side-gate bias. Detailed analysis on a 27 nm x 78 nm (width x length) device show SS decreasing from 115 mV/dec at 400 K to 90 mV/dec at 300 K and down to 36 mV/dec at 100 K, DIBL decreasing by approximately 10 mV/V for each 100 K reduction in operating temperature, and Vt increasing from 0.42 V to 0.61 V as the temperature is reduced from 400 K to 100 K. Vt can be adjusted from ~ 0.3 V to ~ 1.1 V with ~0.3 V/V sensitivity by depletion or accumulation of the body of the device using Vside. This high level of tunability allows electronic control of Vt and drive current for variable temperature operation in a wide temperature range with extremely low leakage currents (<10-13 A).


I. INTRODUCTION
LECTROSTATIC control of the potential barrier between the source and the drain of metal oxide field effect transistors (MOSFETs), and the emitter and collector of bipolar junction transistors (BJTs) determine the minimum feature sizes that can be successfully implemented for a given temperature of operation. Since the charges controlling the barrier height in MOSFETs are electrically isolated from the channel, there is no need for continuous charge injection from the control terminal, unlike BJTs. Ultra-thin-body silicon on insulator (SOI) [1]- [5], FinFET [6]- [9], tri-gate [10]- [15], gate-all-around [16]- [23] and multi-gate [24], [25] structures provide significant improvements in electrostatic control of the source-barrier in MOSFETs and suppress or eliminate the interface leakage currents [26]. Thin-body SOI and gate-all-around devices suffer from floating body effects [27], [28], where majority carriers trapped in the active region reduce the source-barrier (similar to charging of the base in BJTs) and cause soft errors. The active regions of bulk MOSFETs have good electrical and thermal contact with the substrate, allowing for efficient charge and heat removal. Electrostatic control of the source-barrier using substrate/body [23], [29]- [36] or back-gate biasing [37]- [39] allows for dynamic control of threshold voltage. In the case of narrow channel devices, an independently controlled sidegate structure that surrounds the body of a bulk MOSFET can be used to accumulate the body of the device and increase electrical coupling of the body to the channel, increase the source barrier and suppress short-channel effects (Fig. 1). We had first reported a side-gated MOSFET structure with silicon nitride (Si3N4 / Si3+xN4) side-gate dielectric and field isolation (compatible with removal of sacrificial SiO2 using HF to open tunnels and release structures) as a very-low leakage device that can be monolithically integrated with micro-/nanofluidics for high-sensitivity sensors for sequencing of biomolecules [40], [41]. Noticing the success of these devices in suppressing interface leakage currents (below 1 fA), improvements in drain induced barrier lowering (DIBL) and subthreshold slope (SS), and extreme control of threshold voltage (Vt), we fabricated higher-performance versions of these devices with p+ doped side-gates, SiO2 side-gate dielectrics, and SiO2 field isolations for accumulated body operation. These accumulated-body devices show dramatic Vt tuning and improved performance characteristics [42]- [45].
Transistors are thermal devices; the barrier height, the energy distribution of the carriers in the source and drain reservoirs and lifetime of trapped charges [46] depend on temperature. Carrier mobilities also increase with reduced temperature [23], [24], [47]- [49]. Hence, transistors can be operated with lower power and at a higher speed under lower temperatures. While high temperature operation is necessary for certain applications [50]- [53], cryogenic operation of high-performance VLSI circuits has been considered for a long time [23], [24], [47]- [49], [54]- [58]. Recent advances and growing interest in quantum computing have also led to renewed interest in cryogenic electronics for peripheral circuitry. However, significant changes in the operation temperature of the whole or part of the circuit introduces additional complexity in VLSI design and in computer architecture [59]- [61]. In this work, we characterized accumulated body devices in the 100 K to 400 K range, observed the performance characteristics, and explored the ability to dynamically tune Vt as the temperature is changed and the temperature range these devices can reliably operate at.

II. DEVICE STRUCTURE AND FABRICATION
The narrow-channel accumulated body nMOSFETs were fabricated using a conventional bulk silicon process, with additional steps to form the p+ doped side-gate structure and its contact. The side-gate structure is formed around the body using a side-wall process [44], [62]. The side-gate contact is formed in the same etch step by using a lithographically defined region slightly offset from the active region. The side-gates are isolated from the body by 9 nm thermally grown SiO2 and the top-gate is isolated from the active area by 3.9 nm thermally grown SiO2. The body is doped with 1×10 17 cm -3 boron, the side-gate with 1×10 20 cm -3 boron, the source and drain with 1×10 20 cm -3 phosphorous using ion-implantation. Details of the device fabrication, room temperature electrical characterization and simulation results, including high temperature behavior, can be found in [43], [44], and [62].

III. ELECTRICAL CHARACTERIZATION
All the experiments were carried out using an Agilent 4156C Parameter Analyzer between 100 K and 400 K in 25 K intervals in a Janis cryogenic probe station under vacuum, in dark. The characteristics presented here are from measurements performed on a device with width (W) × length (L) = 27 nm ×   (Fig. 2 and Fig. 3).
The body/side-oxide interfaces of these devices are in accumulation, even with Vside = 0 V since the side gates are p+ doped (unlike [40], [41]), thus suppressing recombination at the interface defects, blocking interface leakage currents, and reducing the depletion depth under the active region. Negative bias on the side-gate increases the hole concentration at the side-interfaces, shrinks the depletion depth further, increasing the electrostatic control of the body and suppressing control of the drain potential on the source barrier [41], [44], hence, improving DIBL and SS and increasing Vt.
The sensitivity of Vt to temperature (ΔVt/ΔT) is significantly reduced for negative side-gate bias while sensitivity of Vt to Vside (ΔVt/ΔVside) decreases slightly with reduced temperature as shown in Fig. 4(a) and (b). Subthreshold slope (SS), drain induced barrier lowering (DIBL= ∆ /∆ ), and maximum transconductance (gm) show exponential responses to Vside and a linear response to temperature [ Fig. 4(c)-(h)]. Negative sidegate bias increases Vt linearly [ Fig. 4(b)], significantly more than the change caused by temperature in 100 K to 400 K range [ Fig. 4(a)]. The observed reduction in drive current [ Fig. 4(i)-(l)] appears to be mostly due to increase in Vt for high drain biases. The saturation current (ID-sat) is directly proportional to temperature at lower gate voltages and inversely proportional to temperature at higher gate voltages, and insensitive to temperature for VG ≈ 1.35 V [ Fig. 2 (inset) and Fig. 4(i)]. This is due to the interplay of increased carrier injection over the source-barrier and reduced mobility with increasing temperature [63]. The response of ID-sat to Vside is monotonous [ Fig. 4(j)].

IV. THRESHOLD VOLTAGE TUNING
Accumulated body MOSFET offers an independent control through the side-gate which can be used to achieve a certain threshold voltage at different operation temperatures or to compensate for threshold drifts in unwanted local hotspots. The approximately linear response of Vt to Vside and T (Fig. 4) can be used to predict Vside values required to maintain a constant Vt in a wide temperature range (Fig. 5).
The Vt sensitivity to side-gate bias varies only slightly as a function of temperature, from ~ -308 mV/V at 400 K to ~ -278 mV/V at 100 K, between -2 and +0.5 V side-gate bias. This side biasing sensitivity of ~ 300 mV/V allows for threshold voltage      6). We then repeat this procedure to estimate Vside vs T relationships for any desired Vt values (Fig. 7). To validate our procedure, we repeated the ID-VG measurements between 100and 400 K while applying the calculated Vside for each temperature to tune Vt to example target values of 0.5 V, 0.7 V, and 0.9 V. Fig. 8 shows the resulting Vt to be very close to the target values. Each I-V was performed once with the calculated Vside, after the previous one, with no need for any adjusting iterations, indicating minimal charge trapping on the side-gate dielectric, SiO2 and Si/SiO2 interfaces.

V. SUMMARY
Temperature dependent electrical characteristics of narrow side-gated accumulated body MOSFETs in the 100 K and 400 K range are presented. The measurements show strong and very stable temperature and side-gate bias dependence of the transistor characteristics. Subthreshold slope, drain induced barrier lowering, threshold voltage, and leakage current, all exhibit significant improvements with decreasing temperature and side-gate bias, due to mitigation of short-channel effects. Threshold voltage can be tuned with ~ -300 mV/V sensitivity by side-gate biasing, with a fairly linear response. Hence, it is relatively easy to maintain a constant threshold voltage in a wide temperature range or dramatically change the threshold voltage in part or the whole circuit by adjusting the side-gate biases. Excessively negative side-gate biases are expected to result in degradation of the current drive, due to increased surface roughness scattering, which are more pronounced at lower temperatures [64].
Since the depletion depth and the threshold voltage are controlled by the side-gate bias, an undoped body can also be used, reducing any threshold voltage variations due to random dopant fluctuations [65]. Furthermore, the depletion region can be reduced significantly more than what could be achieved with body doping or biasing and the threshold voltage can be increased above what is achievable by doping body or body biasing. The additional electrostatic control over performance parameters is expected to enable reliable circuit operation in a wide temperature range.