Efficient Integration of Three-Phase Step Voltage Regulators in the Z-Bus Power Flow Method

—This paper presents a comprehensive three-bus equivalent circuit model of three-phase step voltage regulators (SVRs). The proposed model can accurately simulate any SVR configuration and can be efficiently integrated in the Z-bus power flow method. Its distinct feature is that the taps are simulated outside the Y BUS matrix in the form of current sources. As a result, the re-factorization of the Y BUS matrix is avoided after every tap change reducing significantly the computational burden of the power flow analysis. Furthermore, possible convergence issues caused by the low impedance of SVRs are addressed by introducing fictitious impedances, without, however, affecting the accuracy of the model. The proposed SVR model is validated in the IEEE 4-Bus and an 8-Bus network, while its performance is further investigated in the IEEE 8500-Node test feeder.


Introduction
TEP voltage regulators (SVRs) are widely applied to low-(LV) and medium-voltage (MV) distribution networks to maintain voltages within permissible limits. They consist of autotransformers with adjustable turn ratios connected in several configurations e.g open-delta, closedelta, wye [1].
Several methods have been proposed in the literature for the integration of SVRs in the power flow calculation [2]- [4]. More specifically, the authors in [2] and [3] propose a mathematical formulation relating the primary and secondary voltages and currents, which is solved using the backward/forward sweep (BFS) method. Furthermore, in [4], the SVR equations are directly integrated in the Jacobian matrix. However, these approaches are not applicable to the Z-Bus power flow method since the SVR equations of [2]- [4] are not compatible with the formation of YBUS matrix. The Z-Bus power flow approach is a fixedpoint iterative method, which is widely applied in distribution network applications, due to its high robustness, fast convergence, ease of implementation and low computation time [5]- [9]. Therefore, accurate and computationally efficient modelling of SVRs is significant in order for the Z-Bus method to maintain its superior characteristics.
Several SVR models have been proposed in the literature so far, to be implemented in the three-phase implicit Z-Bus power flow. A comprehensive SVR model is proposed in [ configurations, while an open-delta SVR model is proposed in [10]. Although the aforementioned models are applicable in the Z-Bus power flow approach, the tap variables of SVR are simulated in the YBUS matrix of the network. As a result, the re-factorization (or inversion) of the YBUS matrix, which is the most time-consuming action of power flow is required to be executed after every tap variation.
The compensation technique is usually implemented in the ZBUS power flow to avoid the re-factorization of the YBUS matrix every time that one or more elements change [11]. According to this technique, the variable elements are modeled as fictitious current sources outside the YBUS matrix, thus the YBUS matrix remains always constant. Τhis technique is applied in [7] and [11] to simulate transformers equipped with on-load tap changer (OLTC) in balanced networks (using single-phase power flow) and by the authors in [12] to simulate three-phase OLTC transformers in Yg-Yg configuration. However, in case of the SVRs, the implementation of the compensation technique results in the divergence of the power flow, due to the small impedance of SVRs. Similar conclusions about the divergence issues associated with the modeling of SVRs are derived in [13].
This paper proposes a novel model, which overcomes the aforementioned divergence issues. The proposed model consists of a 3-bus equivalent circuit, which presents the following distinct characteristics: • It simulates the taps of SVR as fictitious current sources outside the YBUS matrix, thus avoiding its continuous refactorization after every tap variation. This property is very important in several real-time distribution management system (DMS) applications that require sequential tap variations e.g state estimation [14], optimal power flow (OPF), Volt/Var control (VVC), optimal feeder reconfiguration (OFR) [11], voltage stability analysis, heuristic optimization [15]. With the proposed 3-Bus SVR model, the DMS applications could be significantly accelerated.
• It is generic and can be applied in all SVR configurations i.e., wye, open-delta, closed-delta and types of SVRs i.e., Type A and Type B. • The proposed model presents accurate power flow results since the applied equations are derived considering the exact three-phase SVR circuit. Simulation results confirm that the proposed model outputs identical power flow results with OpenDSS and Simulink. • Although the taps are simulated in the form of current sources, the convergence of power flow is not compromised. Simulation results in Section 6.2 indicate that the proposed model presents identical convergence speed with the model of [1], which implicitly considers the taps inside the YBUS matrix. The rest of the paper is structured as follows: Section 2 explains the difference between the impedance value of an autotransformer and a two-winding transformer. Section 3 presents the proposed SVR model, while Section 4 explains how it is integrated in the Z-Bus power flow. Section 5 validates the proposed SVR model against Simulink and OpenDSS. Finally, Section 6 tests the performance of the proposed SVR model, while Section 7 concludes the paper.

Impedance of autotransformers
Before we proceed with the analysis of the proposed SVR model, it is important to clarify the difference between a two separate winding transformer and an autotransformer. Fig. 1 depicts an ideal two-winding transformer and an ideal autotransformer. The impedances of the transformers are denoted as Z2wT and Zauto and they include the total leakage impedance of the primary and the secondary winding referred to the secondary winding. The primary voltage (V1), the secondary voltage (V2) and the number of turns of the primary windings (N1) are identical for both transformers. Voltages and turn numbers for the two types of transformers can be determined according to (1) and (2). (1) It can be observed that the number of turns of secondary windings (N2wT and Nauto) differs for the two transformer types. Furthermore, assuming that the two transformers have an equal magnetic reluctance, the corresponding impedance ratio for the two transformer types is given by (3).   Fig. 2 depicts the impedance ratio of the two transformer types with respect to the output/input voltage ratio. The figure is obtained using (4) for an output/input voltage ratio between 0.9 and 1.1, which is a typical voltage range for SVRs. It can be observed that the autotransformer presents significantly lower impedance than the two-winding transformer. As a result of the low impedance of the autotransformer, the ZBUS power flow diverges when the compensation technique is applied to the SVR modeling [13]. and − do not affect the power flow results since they are connected in series with opposite signs, thus they cancel each other. Nevertheless, they significantly enhance the power flow convergence, enabling the compensation technique to be applied in the SVR modeling.  By applying simple circuit analysis in Fig. 4, (5a) and (5b) are derived:

Proposed SVR model
where the matrices , , are defined in Tables 1 and 2 for all types and configurations of SVRs. is a 3x3 identity matrix. Eq. (5a) is used to calculate the currents ( , ) and voltages ( , ,) between the nodes p-m, while (5b) is employed to calculate the current ( ) flowing through the primary windings ( ). Note that (5a) and (5b) are generic and can be applied to any SVR by simply modifying the parameters , ,  Table 1 are related to the tap ratios ( ) as follows [2]: The square matrix in (5a) includes the matrix , which is not constant due to the tap variations. Therefore, it is moved outside the square matrix and (6a) is obtained, where the current sources , are given in (6b).
Finally, the voltages and currents between the nodes m-s are expressed in (7), where the matrix is given in Table 2.
Eqs. (6) and (7) can be comprehensively expressed in the form of an equivalent circuit as shown in Fig. 5. The parameters of the equivalent circuit for both types of SVR are given in Tables 1, 2 As shown in Table 3, the current sources depend on the matrices , . To ensure the convergence of the power flow, the values of these matrices should be sufficiently small so that the current sources do not take an extremely large value. That is achieved by selecting a sufficiently large value of . Essentially, the role of is to enhance the convergence by artificially increasing the value of .     Table 3 Current sources for the two types of SVR

Implementation of the proposed SVR model in a 4-Bus network: An example
In this section, the implementation of the proposed model is practically explained in the 4-Bus network of Fig. 6a. A closed delta SVR of type A is connected between the nodes 2-3.
is the SVR impedance, while 12 and 34 for = { , , } are the line impedances connecting the buses 1-2 and 3-4, respectively. The conventional SVR configuration is shown in Fig. 6a, while the proposed SVR model is depicted in Fig. 6b. As shown, the proposed SVR model has an additional fictitious bus 5. Note that no load is connected to this fictitious bus.
The square matrix of (8) includes the 3x3 admittance matrices of the lines between the buses 1-2 ( ,) and 3-4 ( ) as well as the 3x3 matrices and calculated according to The equation system (8) is then solved with the implicit ZBUS method, as described in [5] and [6]. Selecting a sufficiently large value of , the compensating currents in (9) are adequately small to ensure the convergence of the power flow.

IEEE 4-Bus network with 1 SVR
The proposed SVR model is applied in the ZBUS power flow method of [5] and the results are validated against Simulink and OpenDSS in the IEEE 4-Bus network [17]. Some clarifications about the applied parameters are provided below: • The unbalanced loads of [17] are used in this paper. In Open-Delta and Closed-Delta configuration the loads are phase-to-phase connected, while in wye configuration they are phase-to-neutral.
• The SVR is placed in the position of the transformer, between the buses 2-3 [17]. The impedance of the SVR ( ) is calculated based on the data of the single-phase two-winding transformer given in [17], which has the following parameters:  Table 4 for the SVR of type A, and in Table 5 for the SVR of type B. Indicatively, only the phase-to-phase (or phase-to-neutral) voltages of the 4 th node are depicted here. The remaining nodes present similar accuracy. As shown, the results of the proposed approach are in full agreement with those of Simulink and OpenDSS confirming the accuracy of the proposed model.  The proposed SVR model is further validated in the 8-Bus network of Fig. 7, consisting of 3 SVRs and 4 unbalanced constant impedance loads. It is a 4-wire network with the following assumptions: 1) every bus is considered perfectly grounded, 2) the mutual impedance between the neutral and phase conductors is zero. The parameters of the network are quoted in Table 6, while the loads are given in Table 7. The taps of SVRs for the simulated configurations are presented in Table 8.

8-Bus network with 3 SVRs
The proposed approach is compared against Simulink and the results are presented in Table 9. Indicatively, only the voltage magnitude of the three phases of bus 8 are depicted, nevertheless, the remaining buses present similar accuracy. In Table 9, the results of the proposed approach are presented in regular font, the results of Simulink in bold, while the results of OpenDSS in red color. As shown, although the network consists of 3 SVRs, the proposed model produces almost identical steady-state power flow results with Simulink and OpenDSS confirming its accuracy.

Performance of the proposed model
The performance of the proposed SVR model is tested in the IEEE 8500-Node network. The topology of IEEE 8500network is shown in Fig. 8. It includes originally 4 SVRs and 4 capacitor banks. For the sake of simplicity, all capacitor banks are considered OFF. SVR 1 is connected in wye configuration, SVR 2 in open delta configuration, while SVRs 3 and 4 are connected in closed delta configuration. SVR 1, SVR 2, SVR 3 and SVR 4 are connected between the buses 1-2, 405-406, 1057-1058 and 1311-1312, respectively. To get a sense about the position of each bus inside the network, their distance from the substation is presented in Fig. 9. More details about the data of the network e.g lines, loads are provided in [17]. All buses of the network are considered perfectly grounded.

Convergence properties of the proposed SVR model
The convergence characteristics of the proposed model are presented here, with respect to the values of the additional impedance Zadd introduced in Section 3. • For low values (see Fig. 10a) the Z-Bus power flow diverges. This is expectable due to the large values of , (see Table 2), which in turn increase unacceptably the current sources of Fig. 5 (see Table 3).
• The algorithm presents fast convergence for all ≥ 0.5 , as shown in Fig. 10b. Thus, can be arbitrarily selected over a very wide range of values.
• The algorithm converges to the same solution for all ≥ 0.5 . This is logical since an impedance − is connected in series with , canceling completely the influence of .

Comparison of the proposed SVR model against the conventional 2-Bus model of [1]
The performance of the proposed SVR model is further validated against the model presented in [1] using the IEEE 8500-node test network. Moreover, a comparison between the two models with respect to the convergence speed is carried out.
The convergence of the 4 SVRs throughout the iterative power flow process is depicted in Figs. 12-15 for varying taps. More specifically, the tap variables are changing every 30 iterations according to Table 10. At the first iteration, a flat start was considered. The value of (see Section 3) of all SVRs is arbitrarily selected equal to = 5j. As expected, the two models converge to exactly the same solutions with the same convergence speed. Therefore, it is confirmed that the adoption of equivalent current sources for expressing the tap variables instead of including them into the YBUS matrix, does not affect the convergence of the power flow, if a suitable value of is selected. A huge difference exists in the computation time between the proposed and the model of [1], as result of the refactorization of the YBUS matrix from the model of [1] after each tap change. More specifically, when the proposed SVR model is applied, the total computation time of the power flow process of Figs. 12-15 is 45s (namely 90 iterations x 0.5s/iterations). It is pointed out that the initial YBUS factorization is not counted in the computation time since it is usually executed offline. On the opposite, when the SVR model of [1] is applied, the total computation time is 177s. Please note that the computation time of each matrix factorization is 66s measured in Matlab. The additional computation time of ref. [1] is caused from the YBUS factorizations that are required to be executed at 31 th and 61 th iterations as a result of the tap variations. It is reminded that the two-bus equivalent model of [1] expresses the tap variables inside the YBUS matrix, thus, every tap change requires the execution of YBUS factorization. A summary of the computation time of the proposed model and the model of [1] is given in Table 11.    Fig 12. Convergence process of SVR 1, when the taps change every 30 iterations, according to Table 10.

Fig 13.
Convergence process of SVR 2, when the taps change every 30 iterations, according to Table 10.

Fig 14.
Convergence process of SVR 3, when the taps change every 30 iterations, according to Table 10.

Fig 15.
Convergence process of SVR 4, when the taps change every 30 iterations, according to Table 10.

Conclusion
This paper presents a novel 3-Bus equivalent circuit for modeling three-phase SVRs for the ZBUS power flow. The model is applicable in all SVR configurations. Its advantage is that the tap variables are expressed in the form of current sources outside the YBUS matrix, avoiding its re-factorization or inversion after each tap change. The proposed model has been compared against the conventional SVR model, (expressed as a 2-bus equivalent circuit) offering significant speed up in applications, where continuous tap variations are required. The proposed SVR model can constitute an important simulation tool in several DMS applications such as state estimation, OPF, VVC, OFR, voltage stability, heuristic optimization, in which the power flow is executed multiple times in a specific time with continuously varying tap settings.