Understanding the Input Signal Frequency Effects on the Resistive Window of Memristors

— As theoretically predicted by Prof. Chua, the input signal frequency has a major impact on the electrical behavior of memristors. According with one of the so-called fingerprints of such devices, the resistive window, i.e. the difference between the low and high resistance states, shrinks as the frequency increases for a given input signal amplitude. Physically, this effect stems from the incapability of ions/vacancies to follow the external electrical stimulus. In terms of the electrical behavior, the collapse of the resistive window can be ascribed to the shift of the set/reset voltages toward higher values. Moreover, for a given frequency, the resistance window increases with the signal amplitude. In this letter, we show that both phenomena are the two sides of the same coin and that can be consistently explained after considering the snapback effect and a balance model equation for the device memory state.


I. INTRODUCTION
CCORDING to [1] and [2], a memristive device exhibits three major fingerprints: i) a pinched hysteresis loop in the current-voltage (I-V) plane, ii) the decrease of the hysteresis lobe area as the input signal frequency increases, and iii) the shrinking of the pinched hysteresis loop to a single-valued function when the frequency tends to infinite. In terms of the resistive switching (RS) mechanism, the latter two points can be understood as the mutual approach of the low (LRS) and high (HRS) resistance states as the frequency increases. Not only the signal frequency takes part in this problem but also its amplitude needs to be considered. As is well known, for a fixed frequency, the magnitude of the hysteretic current-voltage (I-V) loop increases as the signal amplitude increases (see Fig. 1(a)). In practice, the transitions occur at two voltage levels often referred to as the set (V S ) and reset (V R ) voltages which are regarded as fixed values [3]. Similarly, the I-V loop increases as the signal frequency decreases (see Fig. 1(b)) and for a very high frequency, the I-V curve collapses to a purely resistive behavior. The ratio between the LRS and HRS currents measured at a low fixed bias is referred to as the resistive window of the device and  when properly normalized to unity as its memory state window. Then, one can talk about the collapse of the memory window when the input signal amplitude is decreased and the frequency increased [3]- [5]. It is clear that both aspects of the phenomenon have the same root, i.e. the ion/vacancy displacements within the insulating layer and the formation and rupture of an atomic-size conducting bridge in between the electrodes [6]- [8]. Physically, the collapse of the memory window can be attributed to the incapability of ions/vacancies to follow the input signal [9], [10]. Electrically, the effect is linked to the shift of the transition voltages, V TS and V TR , toward higher values. These issues have been thoroughly investigated in the past for constant and ramped voltage input signals [11]- [14] but a theoretical approach able to deal with arbitrary input signals is still an almost unexplored terrain.
In this letter, the effects of the input signal frequency and amplitude on the hysteretic I-V curves of memristive devices are investigated. The memory window collapse is demonstrated for HfO 2 -based MIM structures. On the basis of Chua's theory, a simple phenomenological memristor model formed by two coupled equations is proposed. The model takes into account the snapback effect in the I-V characteristic and assumes a dynamic balance-type equation for the memory state of the device. We show that the proposed approach provides a consistent framework for understanding the role played by the signal frequency and amplitude applied to memristors.

II. DEVICES AND EXPERIMENTAL DETAILS
The devices used in this work are TiN(200m)/Ti(10m)/ HfO 2 (10nm)/W(200nm) structures with area 5×5µm 2 . The input signal was applied to the top electrode with the bottom electrode grounded. Details about the device fabrication and electroforming processes can be found in [12], [13]. Two kinds of ramped voltage experiments were carried out varying specific parameters in each case. In the first experiment (see Fig. 1(c)), the maximum positive voltage amplitude was ranged from 0.4V to 1.1V (RR~0.3V/s) while the maximum negative amplitude was fixed to -1.5V (RR~0.4V/s) in order to induce the complete reset of the device after each cycle. RR is the ramp rate. In the second experiment (see Fig. 1(d)), RR was varied from 1V/s to 10 6 V/s keeping the positive and negative maximum voltage amplitudes fixed to 1.1V and -1.4V, respectively. As illustrated in Figs. 2(a) and 3(a), the median of the I-V curves shown in Figs. 1(c) and 1(d) were corrected for the snapback and snapforward effects (V-IR S ) using a series resistance R S [15]- [17]. Figure 2(b) shows the dependence of V TR on R S for the different applied signals. The crossover point indicates the optimum value for R S . Regardless of the signal amplitude, the transition voltages are approximately the same (V TS =-V TR 0.5V) for R S 450Ω. Figure 2(c) shows the progressive increase of the memory window with the signal amplitude. In case of the frequency variation, V TS,TR are no longer constant (see Fig. 3(a)) and the cycle-to-cycle variability (C2C) must be taken into account. Figure 3(b) shows the weibits for the individual V TS and V TR values. Remarkably, both data sets can be fitted using the Burr's XII (also called clustering) distribution [18]: where F is the cumulative distribution function, α S,R the clustering, β S,R the shape, and V TS,TR the scale (transition voltages) parameters for set and reset, respectively. The obtained fitting parameters values are β S =75 with 0.35<α S <2.0 and β R =65 with 0.45<α R <1.3. While β takes into account the intrinsic C2C variability, α is related to the extrinsic one (different initial conditions for HRS and LRS). Notice that for

→, (1) yields the Weibull distribution. Figures 3(c) and
3(d) show, respectively, that V TS,TR and R S linearly increase with ln(RR). While the first result is a well-known experimental observation [19], [20], the second one points out that R S is similarly affected by RR. This is not surprising since both behaviors are ultimately ruled by the same mechanism, i.e. the ion/vacancy displacements [21]. This indicates that R S or at least part of R S is associated with the filamentary structure itself [16] and should not be regarded as a completely external artifact [15]. Finally, Fig. 3(e) shows the collapse of the resistive window with RR as predicted by Chua. Notice the asymmetric reduction of the resistive window largely caused by the R S effect on the LRS current. As it will be discussed next, both effects shown in Figs. 2 and 3 can be interpreted as the two sides of the same coin.

III. MODEL DESCRIPTION AND DISCUSSION
In this Section, a simple phenomenological model which contains all the ingredients necessary to understand the collapse of the resistive window is presented. The first equation, which is related to the electron transport and which accounts for the snapback/snapforward effect discussed above, is expressed as: where (g)=g min (½-g)+g max (½+g) is the constriction conductance, -½g½ the memory state, V C the voltage drop across this constriction, V the applied voltage, and g min and g max fitting parameters for the minimum and maximum conductances, respectively. From (2), the I-V curve reads: (3) expresses that the behavior of the I-V characteristic is dictated by two frequency-dependent factors, G C and R S . The second equation deals with the memory state of the device [22] and is expressed in terms of the low voltage-normalized conductance g as a symmetric balance model: where τ S,R are characteristic times associated with the set and  reset transitions. Assuming ion/vacancy hopping transport [23], [24]: where τ 0S,0R and V 0S,0R are fitting parameters of the model. Remarkably, (4) can be represented by the equivalent circuit model shown in Fig. 4(a), where g is the current flowing through the circuit. For the sake of simplicity, in what follows, identical τ S,R parameters will be considered for both positive and negative biases. Figures 4(b) and 4(c) show the hysteretic behavior of g for sinusoidal signals with different amplitude and frequency. Notice how the resulting hysterons or memory loops agree with the experimental results reported in Section II. More in detail, Figs. 4(d) and 4(e) illustrate simulated I-V curves using (3) and (4). Importantly, to our knowledge, analytic results for a timevarying signal in (4) can only be found for the case of a linearly increasing or decreasing positive and negative ramps. Again, for the sake of simplicity, let's consider only the set region of the device. Solving (4) for V C =RRt, yields the double exponential expression: where g 0 =g(t=0) is the initial memory condition. Considering the inflection point of (6), d 2 g/dV C 2 =0, as the reference transition voltage, we obtain: which provides the linear relationship shown in Fig. 3(c). For our devices (HfO 2 ), V 0S =1.3·10 -2 V and τ 0S =2.97·10 9 s are obtained. Moreover, for a cycled ramped voltage signal with maximum amplitude V AMP and frequency f, V C =4V AMP ft, so that from (6) we can look for the initial condition g 0 required for a stationary loop as g(1/4f)=0. This simple exercise provides the amplitude of the memory window g as a function of V AMP and f (see Fig. 4(f)): (8) which, again, is in total agreement with the expected phenomenology for memristive devices.

IV. CONCLUSIONS
In this letter, the dependence of the memory state (resistance) window on the input signal amplitude and frequency was investigated. It was shown that the behavior of the I-V characteristic of HfO 2 -based memristors can be understood as the combined action of two frequency-dependent factors, i.e. a series resistance effect and a phase lag effect in the diffusive movement of ions/vacancies.