Virtual Shifting Impedance Method for Extended Range High-Fidelity PHIL Testing

A novel power hardware-in-the-loop interface algorithm, the virtual shifting impedance, is developed, validated, and demonstrated in this article. Building on existing interface algorithms, this method involves shifting a part of the software impedance to the hardware side to improve the stability and accuracy of power hardware-in-the-loop setups. However, compared to existing approaches, this impedance shifting is realized by modifying the command signals of the power amplifier controller, thus avoiding the requirement for hardware passive components. The mathematical derivation of the virtual shifting impedance interface algorithm is realized step by step, while its stability and accuracy properties are thoroughly examined. Finally, the applicability of the proposed method is verified through power hardware-in-the-loop simulation results.


I. INTRODUCTION
H ARDWARE-IN-THE-LOOP (HIL) methodologies have been proven capable to de-risk and accelerate the deployment of novel power system components, with power hardwarein-the-loop (PHIL) adopted for power components and controller hardware-in-the-loop (CHIL) for controls validation [1].However, the increasing complexity brought on by the paradigm shift in power system operation through the increased incorporation of distributed generation and digitization warrants more rigorous validation under extended range of scenarios and corner cases to ensure a secure operation under high level of expected uncertainty.
For the PHIL simulation case particularly, a power amplifier (PA) unit is required to interface the power hardware device with the system designed in the digital real-time simulator (DRTS) [2], a fact that can introduce additional dynamics to the original system and can cause instabilities and inaccuracies in the PHIL setup.Indeed, for the results of the PHIL simulation to be credible, a proper coordination of the employed devices (e.g., DRTS, signal processing units, PA, etc.) needs to be ensured through the use of appropriate PHIL interface algorithms (IAs) [2].The PHIL-IA basically consists of the PHIL coupling structure (PCS) and the PHIL interface control (PIC).The PCS corresponds to the circuit models to be utilized within the PHIL-IA, one representing the software side, and one representing the the hardware side.Each PCS inherits to the total PHIL topology different stability and accuracy properties.A review of different PCSs is performed in [2], [3], [4], and [5], with the most widely used being the ideal transformer model (ITM).The main advantages of ITM are, first, the straightforward and simple implementation, and second, its good accuracy, while the main drawback is related to the associated stability issues [5], [6], [7], [8], [9].Alternatively, different coupling structures have been found capable of improving the stability of the PHIL setup, like the partial circuit duplication (PCD).In the PCD method, the impedance between the power grid and the power hardware device is duplicated both on the software and the hardware parts of the simulation.Advanced stability properties are also ensured through the damping impedance method (DIM), which is basically combining the ITM and PCD coupling structures.Nevertheless, despite the fact that the stability properties of the PCD and DIM methods are efficient for a wide range of simulation scenarios, a number of issues related to the difficulty of accurately measuring the impedance in the hardware side and introducing it in the software side make those PCSs challenging to be accurately utilized in practice [10].Another highly stable PCS is the transmission-line model (TLM), which models the assumed one time step delay through the natural propagation delay of a transmission line [11].Even though TLM decouples the computational tasks and separates the two networks, it has limited practical value due to the necessity of adding a hardware resistor that, in turn, might lead to an oversizing of the required amplifier [12].
As previously mentioned, the second aspect of an IA is the PIC, which can be combined with the appropriate PCS to achieve natural coupling between the simulator and the hardware device under test (DUT).Even though the conventional ITM PCS corresponds to straight-forward implementation and very accurate approach, its stability characteristics are limited.These stability criteria are determined by the PHIL setup impedance ratio (IR), with system tending to instability when the software impedance is greater than the hardware impedance [13], [14], [15].To address this issue through the PIC, stability augmentation methods and PHIL control algorithms can be utilized.In fact, a low-pass filter (LPF) is usually employed on the hardware current measurement, which is fed back into the DRTS to close the loop [16], [17].This feedback filtering (FBF) method has been found to be stabilizing the PHIL setup, nevertheless, the utilized LPF reduces the accuracy of the system.To alleviate this need for low-pass filtering, advanced IAs are being investigated, aiming to realize at the same time stable and accurate PHIL testing, e.g., through optimal control approaches [7], interface compensation approaches [8], Smith-predictor based stabilization schemes [15], [18], as well as delay compensation techniques [8], [19], while advanced analysis tools have been also reported, such as discrete domain modeling in [6].Among the various PHIL algorithms that have been proposed to improve stability and accuracy, the delay signal compensation (DSC) method manages to compensate for the delays of the system [8], [19] in a straight-forward manner.Nevertheless, it still requires an LPF on the feedback path to maintain a stable system operation, which compromises its accuracy improvement capability.Methods that improve accuracy by reducing the requirement for LPF have recently been proposed based on the concept of introducing a virtual series or parallel impedance through the interface algorithm or through shifting a part of the software impedance to the hardware side [14], [20], [21], [22], [23], [24].Nevertheless, the introduced virtual impedance in the methods proposed to this day are not part of the original system of investigation and may thus lead to inaccurate results.On the other hand, shifting a part of impedance to the hardware requires having impedances of different values readily available at hand to perform multiple test cases, a stringent requirement for most research laboratories.
To address the above issues, a novel IA, the virtual shifting impedance (VSI) method, is proposed in this article to realize extended-range accurate and stable PHIL testing.The main contributions of the article are summarized as follows: 1) A virtual implementation of the shifting impedance algorithm has been proven to be extending the range of stable PHIL simulations, without a need for additional hardware components.2) At the same time, the VSI has been rigorously proven to be offering a substantially improved accuracy, compared to legacy methods, throughout its range of operation.3) Extensive simulation and PHIL results have validated the proposed VSI algorithm and its superiority compared to legacy methods.Particularly, building on existing IAs [14], [23], this method virtually introduces a shifted impedance through the control scheme of the PA unit to accurately extend the range of stable scenarios to be simulated through the PHIL approach.The mathematical derivation of the VSI method is analytically given, while its stability and accuracy properties are thoroughly examined.Finally, the applicability of the proposed IA is verified through extensive PHIL experimental results.

A. System Modeling and Interfacing
A typical PHIL setup comprises a simulated power network in a DRTS interfaced to power hardware via a PA in a closed-loop configuration enabling testing under a safe and controlled environment.As it was discussed above, a PHIL-IA defines the configuration of the interfacing elements of the PHIL setup.A number of PCSs have been proposed in the literature [2], [3], [22]; however, the voltage-type ideal transformer model (V-ITM) has been extensively preferred over the past decade as it offers acceptable stability and accuracy yet is simple in terms of its implementation.Hence, for the sequel of this article V-ITM will be considered as the PCS of the IAs under discussion, which in fact are focusing on the PHIL control algorithms aspect.
In the V-ITM, the device under test (DUT) is modeled as a current sink in the simulation and the PA acts as a voltage source, as shown in Fig. 1.The appropriate control of the current sink and the voltage source can realize a relatively accurate and stable PHIL setup.The entire PHIL setup, including the simulated and hardware system along with the interfacing components, can be represented as a single-input-single-output (SISO) closed-loop system, whose equivalent block diagram is illustrated in Fig. 2. The system open-loop transfer function F O (s) is given by where T d1 and T d2 represent the time delay of the digital interface in the feed-forward and feedback path, respectively; T FW (s) and T FB (s) represent the signal processing units; T VA (s) and T CM (s) represent the equivalent transfer function of the PA and current sensor, respectively; Z 1 (s) (i.e., R 1 + sL 1 ) and Z 2 (s) (i.e., R 2 + sL 2 ) represent the equivalent impedances in the simulation and hardware side, respectively.
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B. PHIL Stability Analysis
Based on the open-loop transfer function F O (s) of the PHIL closed-loop system in Fig. 2, the system stability can be analyzed by applying the Nyquist stability criterion [25] to the system characteristic equation, which is given by A practical implementation of V-ITM inherently comprises nonidealities compared to that of an ideal theoretical V-ITM interface implementation.These nonidealities include time delay, dynamics of the PA, and the nonunity gain to name a few.While all the characteristics play a role in determining the stability of a closed loop PHIL system, the stability and its analysis is dominated by the ratio of the impedance between the software side and the hardware side-referred to simply as IR.Taking a PHIL system with hardware side impedance of Z 2 = 5 + s0.001 Ω and aggregated time delay of 250μs as an example, Fig. 3 presents the Nyquist plot of the open-loop transfer function of the PHIL system with variable software side impedance (Z 1 ).As can be observed, with the increase in the software impedance, the Nyquist curve tends toward the critical point (−1, 0), representing an unstable system once the critical point has been encircled.Therefore, the system stability is susceptible to variations in impedance and presents a limitation in realization of stable PHIL setups.

C. Methods for Stability Enhancement
With the IR between the simulation and hardware side as a key determinant of the PHIL stability, many research efforts have been devoted to improving the stability of the setup by physically or artificially manipulating the IRs.The approaches adopted for enhancement of stability can be broadly classified into two: 1) approaches that manipulate the interface signals (such as the voltage or current) and 2) approaches that manipulate the impedances of the two systems (hardware or software).Three commonly adopted practices for stability improvement are discussed below, first of which manipulates the interface signal and the latter two the impedance of the setup.
1) Feedback Filtering Method: Most of the times, an LPF is utilized in the feedback path to improve PHIL setup stability [14].The addition of the LPF impacts the current and, therefore, classes under approaches that manipulate the interface signals.While the inclusion of an LPF has proven to improve the stability of the system, lower cutoff frequencies can lead to unacceptable inaccuracies, and the approach also fails to stabilize systems of high IRs.2) Virtual Impedance Insertion Method: In [20], a method of virtual impedance insertion is proposed to reduce the IR between simulation and hardware side.This is achieved by inserting an extract shunt capacitance within the simulated network, thereby, reducing the equivalent impedance of the simulation side.However, the system stability is improved at the expense of deteriorated accuracy, arising from the inserted additional component, especially in cases that appropriate shaping or compensation does not take place.3) Physical Shifting Impedance Method: As the name suggests, a portion of the impedance from simulation side is physically shifted to the hardware side, thereby, changing the IR of the PHIL setup and improving stability in a simple manner.As no additional component is added, theoretically this approach offers no deterioration in accuracy.In practice, as has been reported in [14], the approach still requires the inclusion of an LPF in the feedback path.However, higher cutoff frequency suffice to ensure the stability, and therefore, the deterioration in accuracy is limited.Nevertheless, the required hardware impedance to be incorporated in the hardware system limits the applicability of this method.

III. PROPOSED INTERFACE ALGORITHM
With the limitations of the approaches in literature identified, this article proposes a novel stability enhancement interface algorithm that incorporates the principles of both, the manipulation of interface signals and the manipulation of the IR.The proposed approach is the VSI method.The forward interface signal, voltage in this case, is manipulated in the controller of the PA to represent the voltage after the shifted impedance.This manipulation of the interface signal emulates the physical shifting impedance and thereby improves the stability of the PHIL setup.The practical implementation of the approach is realized through the advanced control capabilities of modern PAs, where a virtual impedance algorithm within the inner control loop can realize the implementation of the VSI method.
As in the modeling description in Section II-A, consider that the initial software system impedance is ( Aiming to shift a portion of Z 1 to the hardware System 2, inspired by [14], and assuming that the ratio of the shifted resistance and reactance is a, with a ∈ (0, 1), then the new software system impedance is Assume the voltage after impedance Z 1n is V D .With the software impedance reduced, the voltage after the original system impedance Z 1 is to be emulated by the PA to realize the virtual shift in impedance and ensure accurate simulation.In fact, the voltage V A can be obtained by subtracting the voltage drop across the shifted impedance R sh = aR 1 and X sh = aX 1 from V D as described in the following equations [26]: This makes it feasible to generate the voltage at the output of the shifted impedance by manipulating the reference voltage of the PA, without requiring the addition of any hardware impedance component in System 2. The steady-state approximation of the virtual impedance implementation, widely used in inverter control schemes, can also be adopted to overcome practical implementation issues [27], [28], [29].The inclusion of the transient (derivative) term in the control action can lead to possible amplification in noise, requiring an LFP that can deteriorate the response of the proposed method.In addition, the incorporation of the derivative term also increases the computational burden significantly.Therefore, ignoring the derivative dynamic term, the reference voltage takes the form V where V A is the manipulated reference voltage of the inner voltage control scheme of the PA, and I A is the current of the hardware system.The implementation of the VSI methodology is depicted graphically in Fig. 4 that is practically implemented in the PA's control card, as shown within Fig. 1.The original impedance of the hardware system remains the same, i.e., Z 2 = R 2 + jX 2 , without requiring the additive physical impedance, as it would in the PSI method case.

IV. STABILITY ANALYSIS
This section presents the stability analysis of a PHIL setup with VSI.First, the transfer function of a PHIL setup with VSI is derived, followed by derivation of the minimum shifted impedance required to ensure stability of any given system.The section further presents analytical stability assessment of PHIL systems with both FBF and VSI methods to establish the effectiveness of the proposed approach.

A. Stability Conditions
The virtual impedance shifting implemented in ( 7) and ( 8) can be further modeled as an equivalent impedance (Z SH ), arising as an additional feedback loop to manipulate the reference signal of the power amplifier.The equivalent block diagram of the PHIL system with VSI method implemented is illustrated in Fig. 5, whose open-loop transfer function is given by (9) shown at the bottom of the next page.
Assuming the transfer functions of signal processing, measurement units and PA as unity and substituting Z SH (s) = aZ 1 (s) into ( 9), the open-loop transfer function of VSI-based PHIL system can be written as Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE I SYSTEM PARAMETERS FOR PERFORMANCE VALIDATION
Accordingly, the system characteristic equation is given by According to the Nyquist stability criterion [25], the minimum PHIL system stability margin is the shortest distance between F * O (jw) and the critical point (−1, 0) in the polar diagram as presented in Fig. 3.The condition for the minimum stability margin is achieved when the real-part of F * O (jw) is greater than −1, and can be represented as ) Using the condition for marginal stability, the minimum VSI ratio a can be determined.Substituting (9) into (12) yields the shifting impedance at marginal boundary for stabilizing the PHIL system.

B. Analytical Stability Assessment
This section presents the stability assessment of the VSI-based PHIL system along with a comparison against the conventional FBF method.As given in Table I, two sets of hardware impedance are employed to emulate different impedance ratios and to assess the stability boundary of the VSI method.The remainder of the PHIL interfacing component parameters have been identified in Table I.The stability performance of VSI (with different shifting IRs) and conventional FBF method (with different cutoff frequencies) for the two impedance sets are investigated with the frequency responses of the open-loop transfer function shown in Fig. 6.
The PHIL system with impedance Set 1 presents a high IR (IR = 5) that requires an LPF with cutoff frequency that is rated below 300 Hz to maintain its stability as presented in Fig. 6(a).However, this stability is achieved at the expense of deteriorated accuracy and limited bandwidth, which degrades the fidelity of the PHIL system.The VSI-based interface can stabilize the system with such high IR with a virtual impedance shifting ratio around 90%, as presented in Fig. 6(b), without the limitation in bandwidth as presented in the FBF method.
The PHIL impedance Set 2 presents a lower IR that can be stabilized by an LPF with higher cutoff frequency (∼1900 Hz) than that required by the PHIL with impedance Set 1, as presented in Fig. 6(c).Although a higher cutoff frequency is utilized, this still limits bandwidth and accuracy.As illustrated in Fig. 6(d), the VSI-based interface can stabilize the PHIL system with a minimum impedance shifting ratio (∼32%).

V. PERFORMANCE VALIDATION
In this section, the performance of the proposed VSI method is validated in simulation.The VSI offers two distinct advantages: 1) extends the range of realizable PHIL setups, not otherwise possible through conventionally available stability enhancement approaches in literature and 2) improved accuracy for PHIL setups where stability can otherwise be achieved by employment of conventional approaches.This section will present two cases: 1) for the extended range of PHIL setups that can be realized and 2) on the enhancement of accuracy.In both cases, the performance of the VSI will be compared to that of the FBF method.The two sets of IR employed in stability analysis are again utilized, as presented in Table I.The following subsections will present the performance evaluation in detail.

A. Extending the Range of Realizable PHIL Setups
The first set of hardware impedance chosen leads to an unstable PHIL setup that remains unstable even with the incorporation of a very low cutoff frequency LPF, i.e., 300 Hz (as shown in Fig. 7).To the best of author's knowledge, the utilized cutoff frequency is less than the lowest reported feedback LPF tuning found in literature, i.e., 350 Hz in [30].The VSI method is able to realize a stable PHIL setup with a software impedance shift of 90% as shown in Fig. 7 (in accordance with the analytical stability assessment presented in previous subsection).This clearly demonstrates the capability of the proposed approach to extend the range of realizable PHIL setups, enabling the validation of novel technologies and controls in broader range of scenarios than feasible with conventional approaches.

B. Accuracy Enhancement
This section evaluates the improvement in accuracy that the proposed VSI approach offers over the FBF method.The second set of hardware impedance is utilized for the implementation of Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.the PHIL setup.For a fair assessment, the accuracy is assessed with the realization of the setup at the boundary of stability, i.e, a marginally stable system.For the FBF method, this is with the incorporation of the LPF with a cutoff frequency that leads to a marginally stable PHIL setup.Similarly, for the VSI approach, the amount of impedance shifted is such that it realizes a marginally stable PHIL setup.
To aid the assessment of accuracy, a metric capable of quantifying the resulted accuracy in steady-state is needed.In this regard, as presented in [8], the power tracking error (PTE) is defined as where P (t) and Q(t) are the active power and reactive power measured at the source of the monolithic system of interest (SoI), respectively.Moreover, P (t) and Q (t) are the active power and reactive power at the source of the simulated PHIL setup under investigation, respectively.
The maximum allowed LPF to stabilize the chosen PHIL setup is 1800 Hz, while an impedance shift of 32% realizes a marginally stable setup for the VSI case.The results of the accuracy assessment in steady state are presented in Table II.As can be observed, the proposed approach outperforms the FBF approach.This demonstrates the enhancement in accuracy that the proposed approach offers over conventional approaches, enabling more accurate PHIL testing of novel technologies and controls.
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C. Applicability: VSI Versus FBF
An additional scenario is also investigated, where a high share of impedance (90%) is virtually shifted to the hardware side.The results are presented in Table II.While it is intuitive that a very stable implementation is realized, it is interesting to note that the accuracy of the approach is deteriorated.However, it should be noted that even with such high percentage of virtual impedance shift, the proposed approach outperforms the FBF approach that is at marginal stability (higher stability through FBF implies use of smaller cutoff frequency, and therefore, higher inaccuracy).To support generalization, the investigation has been repeated for varied IRs from 1 to 2. In that case, the shifting ratio required to stabilize the system increases with the increase in IR, as it was also proven in the stability analysis.However, for all cases considered, the accuracy of the system with 90% shifting ratio is still better than with the incorporation of FBF realizing marginal stability.Hence, for cases considered, the VSI should be chosen for implementation over the FBF, while for much higher IRs, it been proven that VSI is the only viable option.However, the following two factors can limit its employment.
1) Availability of suitable PA: The implementation of VSI required the availability of a power amplifier that allows the manipulation of reference signals through a control card.In case of unavailability, the FBF approach can be adopted within the DRTS.2) Determining a: If the IR of a PHIL setup is not known, determining the minimum shift in impedance can be a challenge for users not familiar with stability analysis.A simple procedure to determine the impedance shift can, however, be adopted.As the accuracy of the VSI with 90% shift is better than the accuracy of FBF, a quick confirmation of stability can be performed at this value.If a stable setup is realized with 90% shift in impedance, the value of shifted impedance can be reduced in decrements of 10%.While this still serves as a trial-and-error approach, it simplifies the process of utilizing VSI and its proven unique features.

VI. LABORATORY VALIDATION
Having established the superior performance of the proposed approach by means of simulations and analytical assessments,  this section establishes its practical applicability through experimental validation.The experiments were undertaken in the dynamic power system laboratory (DPSL) at the University of Strathclyde, Glasgow, United Kingdom.The experimental setup, as shown in Fig. 8, comprises a real-time digital simulator from RTDS technologies, a Triphase 90 kVA voltage source back-to-back converter (TP90 kVA) acting as the PA, and a 256step passive load bank as DUT.An equivalent voltage source with a nominal Line-to-Line ac voltage V S,LL of 0.4 kV and a low X/R ratio grid impedance, as given in Table III, are emulating a low-voltage grid within the DRTS side.The TP90 kVA power amplifier bridges the DUT (i.e., static load bank) and the DRTS.The signal conversion between DRTS and TP90 kVA is achieved by leveraging two signal conversion cards [i.e., giga-transceiver analog output (GTAO) card and giga-transceiver analog input (GTAI) card].The remainder of the parameters for this PHIL setup are presented in Table III.
To realize the V-ITM structure, as shown in Fig. 8, the digital voltage signal V D measured at the point of common coupling of the equivalent network is transmitted to TP90 kVA as its command signal, which is manipulated by the proposed VSI unit, when the latter is enabled.The current response of the passive load bank I A is then measured and transmitted to the DRTS as the command signal for the controllable current source.The digital V D and analog signal I A are recorded by RTDS and Triphase datalogger with a sampling rate of 20 and 16 kHz, respectively.For the validation that follows, the software and hardware side impedances are presented in Table III, selecting an IR greater than 1, which poses a challenge for PHIL stability.The following subsections present a comparative assessment of the FBF and VSI methods, regarding their performance in stabilizing a PHIL setup and maintaining an accurate response.

A. Assessment of the FBF Method
Fig. 9 presents the hardware current signal I A of the FBFaided PHIL setup, which incorporates an LPF with different cutoff frequencies.Before the FBF is enabled, as illustrated in Fig. 9, the hardware side current presents remarkable oscillations, as such the PHIL system tends to instability.When the FBF is enabled, the hardware current presents fewer oscillations compared to the previous case.However, as shown in Fig. 9(a), (c), and (e), only with a significant decrement of the LPF cutoff frequency to the range of 50 Hz, the hardware current of the PHIL setup converges to a sinusoidal response.
Even if an LPF with an extremely low cutoff frequency can stabilize a PHIL, this comes at the expense of the accuracy of the PHIL setup.In particular, as shown in Fig. 10, when the software side voltage source V S,LL witnesses an amplitude step variation from 0.4 to 0.42 kV and a frequency step change from 50 to 50.5 Hz, the active power of the PHIL setup (implemented with FBF with 50 Hz cutoff frequency) presents significant discrepancies compared to the original SoI.In fact, for these two test scenarios, the active power PTEs are 20.67% and 20.86%, respectively.Hence, it is validated that the enhanced stability is achieved at the expense of a reduced PHIL closed-loop system bandwidth and a deteriorated accuracy.The former is attributed to the implementation of the LPF, where an extremely low cutoff frequency is needed to stabilize the PHIL setup.While the latter arises from the nonunity magnitude and nonzero phase response of the LPF, it leads to magnitude distortion and phase lag of the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
PHIL interfacing signals.These attributes significantly limit the applicability of the FBF method in stabilizing a PHIL setup.

B. Performance Evaluation of VSI Method
To validate the effectiveness of the proposed VSI method in stabilizing a PHIL setup, the VSI unit is applied to the PHIL setup, as presented in Fig. 8, while considering different shifting IRs a.The hardware current, software voltage, and active power responses are presented in Fig. 11.As is evident, the implementation of the proposed VSI method mitigates the active power oscillations of the PHIL setup to a lower level compared to the case of the PHIL setup without VSI.Moreover, with the impedance shifting ratio increment, the power signals tend to converge and present fewer oscillations.The VSI-aided PHIL system reaches a stable state once the shifting IR a satisfies the stability criterion defined in (12).As shown in Fig. 11(d) and (e), once the shifting IR is sufficient enough to stabilize the PHIL setup, the higher the shifting IR is, the faster the power signals converge to a stable state.
Furthermore, to demonstrate the capability of the proposed VSI method in withstanding power system transients, an amplitude step variation from 0.4 to 0.42 kV and a frequency step change from 50 to 50.5 Hz are applied to the software side voltage source V S,LL .Once the voltage step change is implemented at t = 0.2 s, as can be observed from Fig. 12(a), the proposed VSI-aided PHIL setup maintains stable operation during the transient, while the active power PTE is 0.31% once the PHIL system reaches a stable state.Note that, as presented in Fig. 12(b), after the frequency step change is triggered at t = 0.2 s, the PHIL active power takes a longer duration to reach a steady state than the SoI.This is attributed to the frequency variation response of the signal processing and synchronization units (i.e., abc to dq, dq to abc, and phase-locked-loop) that are utilized for the realization of the proposed VSI presented in ( 5) and (6).After the transient oscillations, the active power converges to a stable state with an active power PTE 0.33%.Finally, as proven in the previous sections, even with a higher shifted IR, this accuracy should remain at the same levels, thus allowing the selection of the appropriate ratio based on the discussion provided in Section V-C.

VII. CONCLUSION
This article presented the concept of virtual shifting impedance to realize stable PHIL setups.Utilizing the advanced control capability of modern PAs, the software impedance was virtually shifted to the hardware through manipulating the reference voltage signal sent through the DRTS.Through the derivation of the transfer function-based model, the criteria for the minimum shift in impedance to realize stable PHIL setups have been attained.The approach offered a significant advantage over the existing state-of-the-art approach commonly adopted in practice, i.e., the FBF method.The performance enhancement in comparison to the FBF method has been demonstrated through analytical assessment and simulations.The real-world applicability of the approach was proven through an experimental study, with the VSI incorporated within a commercial power amplifier.

Fig. 3 .
Fig. 3. Nyquist plot of the open-loop transfer function of the PHIL system with variable software impedance.

Fig. 10 .
Fig. 10.Grid side active power of LPF-aided PHIL setup that is subject to (a) voltage step change, and (b) frequency step change.

Fig. 12 .
Fig. 12. Grid side active power of VSI-aided PHIL setup that is subject to (a) voltage step change and (b) frequency step change.