Wave Digital Emulation of an Enhanced Compact Model for RRAM Devices with Multilevel Capability

The reliable and compact modeling of RRAM devices is crucial for supporting the development of novel technologies including them. The latter includes a wide range of applications, such as in-memory computing in neuromorphic networks or memristive logic. A major advantage of the considered HfO2- based RRAM devices is their CMOS-compatibility, which allows them to already be utilized in present applications. However, one problem with RRAMs is that their fabrication still leads to device variabilities. This makes it challenging to test the functionality of aspiring technologies utilizing them in an experimental fashion. This work is dedicated to the compact modeling and efficient emulation of 1T-1R RRAM devices. Specifically, we aim to provide an enhanced model, based on the Stanford-PKU model, that can be used on any simulation platform such as SPICE, VERLIOGA, or even standard ODE solvers to simulate multilevel capable RRAM devices. Furthermore, we provide an algorithmic model, based on the wave digital concept, which allows for emulating the considered RRAM device in real-time. Using the latter, we show the hysteresis of our enhanced model to exhibit astounding resemblance with real device measurements.