ML
Publications
- Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies
- Enabling Trust for Advanced Semiconductor Solutions Based on Physical Layout Verification
- CRESS: Framework for Vulnerability Assessment of Attack Scenarios in Hardware Reverse Engineering
- ViTaL: Verifying Trojan-Free Physical Layouts through Hardware Reverse Engineering
- Indonesia-Germany MathCityMap training: Shifting mobile math trails teacher training to a hybrid environment
- Counterfeit Detection by Semiconductor Process Technology Inspection
- Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions
- Automated Defect Inspection in Reverse Engineering of Integrated Circuits
- Boundary Enhanced Semantic Segmentation for High Resolution Electron Microscope Images
- Layout-Only Hardware Trojans: Attack Vectors and a Non-Golden Model Reverse Engineering-Based Counterstrategy