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An Event-Based, Digital Time Difference Encoder Model Implementation for Neuromorphic Systems
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  • Daniel Gutierrez-galan ,
  • Thorben Schoepe ,
  • Juan Pedro Dominguez-Morales ,
  • Angel Jimenez-Fernandez ,
  • Elisabetta Chicca ,
  • Alejandro Linares-Barranco
Daniel Gutierrez-galan
University of Seville, University of Seville

Corresponding Author:[email protected]

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Thorben Schoepe
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Juan Pedro Dominguez-Morales
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Angel Jimenez-Fernandez
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Elisabetta Chicca
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Alejandro Linares-Barranco
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Abstract

Neuromorphic systems are a viable alternative to conventional systems for real-time tasks with constrained resources. Their low power consumption, compact hardware realization, and low-latency response characteristics are the key ingredients of such systems. Furthermore, the event-based signal processing approach can be exploited for reducing the computational load and avoiding data loss, thanks to its inherently sparse representation of sensed data and adaptive sampling time. In event-based systems, the information is commonly coded by the number of spikes within a specific temporal window. However, event-based signals may contain temporal information which is complex to extract when using rate coding. In this work, we present a novel digital implementation of the model, called Time Difference Encoder, for temporal encoding on event-based signals, which translates the time difference between two consecutive input events into a burst of output events. The number of output events along with the time between them encodes the temporal information. The proposed model has been implemented as a digital circuit with a configurable time constant, allowing it to be used in a wide range of sensing tasks which require the encoding of the time difference between events, such as optical flow based obstacle avoidance, sound source localization and gas source localization. This proposed bio-inspired model offers an alternative to the Jeffress model for the Interaural Time Difference estimation, validated with a sound source lateralization proof-of-concept. The model has been simulated and implemented on an FPGA, requiring 122 slice registers of hardware resources and less than 1 mW of power consumption.
May 2022Published in IEEE Transactions on Neural Networks and Learning Systems volume 33 issue 5 on pages 1959-1973. 10.1109/TNNLS.2021.3108047