FORSA: Exploiting Filter Ordering to Reduce Switching Activity for Low
Switching activity in digital circuits depends on the temporal
distribution of the data participating in the operation which directly
influences the interconnect, dynamic power and timing of the system.
This paper proposes an efficient method for reducing both power and
latency of matrix-multiplication operations found in many applications
like convolution neural networks (CNNs). The approach takes advantage of
the unique characterizes of CNN with input stationary for efficient
multiply-add operation. Since most application use reduce accuracy for
MAC, the proposed work assumed 8-bit fixed point representation. As a
demonstrator, CIFAR-10 data set has been used for end to end analysis of
the filters on a 3-ConV with 2-FC model structure. The filters’ were
re-ordered to reduce the switching behaviour between successive weight
fetching. This directly impacts the dynamic power consumption and
miraculously makes the classification activity reduces cross-coupling
capacitance which helps improve timing and noise.