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Novel hybrid low-resource Field-Programmable-Gate-Array time-to-digital-converter architecture
  • +5
  • Diego Real,
  • David Calvo,
  • Mario Manzaneda,
  • Antonio Díaz,
  • Rebecca Gozzini,
  • Juan de Dios Zornoza,
  • Carlos Ricolfe-Viala,
  • Rafael Lajara
Diego Real

Corresponding Author:[email protected]

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David Calvo
Mario Manzaneda
Antonio Díaz
Rebecca Gozzini
Juan de Dios Zornoza
Carlos Ricolfe-Viala
Rafael Lajara


Time measurements are challenging in electronics 1 given their various applications. The main focus lies not in achieving greater precision, as conventional architectures have already reached picosecond levels. Instead, the challenge stems from the use of low resources and the substantial expansion in the number of channels. This study presents a novel architecture for the implementation of TDCs in applications where resources are constrained. The introduced FPGA-based TDC offers a resolution of 415.84 ps, a single-shot precision of 0.45 LSB (186 ps r.m.s), while maintaining a minimal resource occupancy. Built upon a multi-shift phase counter, the TDC is extended with a tap delay using the input delay available in the FPGA hardware input, doubling the resolution of the TDC. The resource utilization is minimized when compared to low-resources state-of-the-art TDCs. The number of LUTs has been reduced up to 102, and the number of registers to 213. Furthermore, the presented TDC exhibits favorable DNL (0.2 LSB) and INL 17 (0.15 LSB). The TDC has been successfully implemented on an Artix7-2 FPGA from Xilinx. This design provides a resource-effective solution for applications requiring high precision and  low resource consumption.
24 Feb 2024Submitted to TechRxiv
27 Feb 2024Published in TechRxiv