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A Fully Configurable Unified FEC Decoder for LDPC, Polar, Turbo, and Convolutional Codes with Row-First Collision-Free Compression
  • +4
  • Yufan Yue,
  • Seungkyu Choi,
  • Tutu Ajayi,
  • Xiangdong Wei,
  • Ronald Dreslinski,
  • David Blaauw,
  • Hun Seok Kim
Yufan Yue
University of Michigan

Corresponding Author:[email protected]

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Seungkyu Choi
University of Michigan
Tutu Ajayi
University of Michigan
Xiangdong Wei
University of Michigan
Ronald Dreslinski
University of Michigan
David Blaauw
University of Michigan
Hun Seok Kim
University of Michigan


This paper presents the first chip implementation of a quad-mode decoder for LDPC, Polar, Turbo, and convolutional codes. It offers 9 fully configurable parameters accommodating arbitrary parity-check matrices up to the size of 8192×16384. It supports a broad range of wireless communication standards such as LTE, Wifi, WiMAX, WiGig, ITU, 5gNR, SDA-OCT, and proprietary codes. Through a novel Row-First Collision Free compression algorithm, LDPC memory usage is dramatically reduced by 89.4%. Furthermore, hardware-sharing techniques optimize memory requirements by an additional 36.9%. Operating at 93.08MHz in LDPC mode, the chip achieves a throughput of 1.62Gb/s/iteration at 239mW, with a normalized energy efficiency of 17.95fJ/bit/check/iteration. Its flexibility far exceeds state-ofthe-art configurable and single-mode designs, positioning it as a front-runner in multi-mode decoding chips.
08 Apr 2024Submitted to TechRxiv
09 Apr 2024Published in TechRxiv