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A 5
  • Yasser Qaragoez
Yasser Qaragoez
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Abstract

In this paper, a 5.8 GHz linear power amplifier (PA) in a 130 nm CMOS process using transconductance linearization technique is presented. The power stage consists of a main amplifier with Class-F load impedance and two auxiliary amplifiers which are biased for weak Class-AB. The proposed configuration increases both the linearity of the PA at high output power levels and the efficiency at back-off powers. The AM-AM and AM-PM nonlinearities of the auxiliary amplifiers cancel the same nonlinearities of the main amplifier at higher output powers. A bypass network is introduced to prevent a positive feedback and common-mode oscillations through the supply path. The PA shows a saturated output power of 23 dBm with 41% PAE and 17dB small-signal gain. Dynamic supply voltage allows a low-power operation with improved efficiency for back-off input powers. For supply voltages of 1.8V, 2.2V, and 3.3V the linear output power and PAE are 12.67dBm, 16.77dBm, and 18.1dBm and 11%, 19.27%, and 20.44%.