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Designing and Implementing a power Efficient BIST in a BCD Multiplier
  • CHRISTY RACHEL SAM
CHRISTY RACHEL SAM
College Of Engineering,Munnar

Corresponding Author:[email protected]

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Abstract

On any chip, the number of transistors doubles every eighteen months according to Moore’s law. When there are more transistors in a circuit, there is a higher probability that one of those transistors will have a fault. To avoid and detect possible errors,testing is required. To test the required circuit, the BIST (Built-in-Self-Test) energy saving design emplos a modified MISR as the ORA (Output Response Analyzer) and a bit-swapping LFSR as the TPG (Test Pattern Generator). In this paper, we select two circuits - a combined circuit and an 8x8 BCD  multiplier as CUT (circuit under test). TPG generates test patters that are fed into CUT, hile ORA evaluates the data generated by CUT and checks for errors in the circuit, and generates a pass/fail signal. This BIST structure detects one of the errors in the circuit.All results are matched to Xilinx ISE Design Suite 14.7 using Verilog and integrated into Vivado 2018.2.