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Cryptensor: A Resource-Shared Co-processor to Accelerate Convolutional Neural Network and Polynomial Convolution
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  • Jin-Chuan See ,
  • Hui-Fuang Ng ,
  • Hung-Khoon Tan ,
  • Jing-Jing Chang ,
  • Kai-Ming Mok ,
  • Wai-Kong Lee ,
  • Chih-Yang Lin
Jin-Chuan See
Universiti Tunku Abdul Rahman (UTAR)

Corresponding Author:[email protected]

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Hui-Fuang Ng
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Hung-Khoon Tan
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Jing-Jing Chang
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Kai-Ming Mok
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Wai-Kong Lee
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Chih-Yang Lin
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Abstract

Practical deployment of convolutional neural net?work (CNN) and cryptography algorithm on constrained devices are challenging due to the huge computation and memory requirement. Developing separate hardware accelerator for AI and cryptography incur large area consumption, which is not desirable in many applications. This paper proposes a viable solution to this issue by expressing the CNN and cryptography as Generic-Matrix-Multiplication (GEMM) operations and map them to the same accelerator for reduced hardware consumption. A novel systolic tensor array (STA) design was proposed to reduce the data movement, effectively reducing the operand registers by 2×. Two novel techniques, input layer extension and polynomial factorization, are proposed to mitigate the under-utilization issue found in existing STA architecture. Additionally, the Tensor Processing Element (TPE) is fused using DSP unit to reduce the Look-Up Table (LUT) and Flip-Flops (FF) consumption for implementing multipliers. On top of that, a novel memory efficient factorization technique is proposed to allow computation of polynomial convolution on the same STA. Experimental results show that Cryptensor achieved 22.3% better throughput for VGG-16 implementation on XC7Z020 FPGA; 95.0% lesser LUT when implementing on XC7Z045 compared to state-of-the-art result. Cryptensor can also flexibly support multiple security levels in NTRU scheme, with no additional hardware. The proposed hardware unifies the computation of two different domains that are critical for IoT applications, which greatly reduces the hardware consumption on edge nodes.
2023Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems on pages 1-1. 10.1109/TCAD.2023.3296375