Abstract—We report the design, implementation, and experimental characterization of an 8-channel EEG recording IC (0.13μm CMOS, 12mm2 total area) with a channel architecture that conducts both the extraction and removal of motion artifacts on-chip and in-channel. The proposed dual-path feed-forward method for artifact extraction and removal is implemented in the analog domain, hence is needless of a DSP unit for artifact estimation, and its associated high-DR ADCs and DACs employed by the state of the art for artifact replica generation. Additionally, the presented architecture improves system’s scalability as it enables channels’ stand-alone operation, and yields the lowest reported channel power consumption among works featuring motion artifact detection/removal.

Following an experimental study on electrode-skin interface electrical characteristics for dry electrodes in the absence and presence of motions, the paper presents the channel architecture, its detailed signal transfer function analysis, circuitlevel implementation, and experimental characterization results. Our measurement results show an amplification voltage gain of 48.3dB, a bandwidth of 300Hz, rail-to-rail input DC offset tolerance, and 41.5dB artifact suppression, while consuming 55μW per channel. The system’s efficacy in EEG motion artifact suppression is validated experimentally, and system-and circuitlevel features and performance metrics of the presented design are compared with the state of the art.