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Cryogenic Embedded System to Support Quantum Computing: From 5nm FinFET to Full Processor
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  • Paul R. Genssler ,
  • Florian Klemme ,
  • Shivendra Singh Parihar ,
  • sebastian brandhofer ,
  • Girish Pahwa ,
  • Ilia Polian ,
  • Yogesh Singh Chauhan ,
  • Hussam Amrouch
Paul R. Genssler
University of Stuttgart

Corresponding Author:[email protected]

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Florian Klemme
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Shivendra Singh Parihar
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sebastian brandhofer
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Girish Pahwa
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Ilia Polian
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Yogesh Singh Chauhan
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Hussam Amrouch
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Quantum computing can enable novel algorithms infeasible for classical computers. For example, new material synthesis and drug optimization could benefit if quantum computers offered more quantum bits (qubits). One obstacle for scaling up quantum computers is the connection between their cryogenic qubits at a few (milli)kelvin and the traditional processing system on chip (SoC) at room temperature ( 300 K). Through this connection, outside heat leaks to the qubits and can disrupt their state. Hence, moving the SoC into the cryogenic part eliminates this heat leakage. However, the cooling capacity is limited, requiring a low-power SoC, which, at the same time, has to classify qubit measurements under a tight time constraint. In this work, we explore for the first time if an off-the-shelf SoC is a plausible option for such a task. Our analysis starts with measurements of state-of-the-art 5 nm FinFETs at 10 K and 300 K. Then, we calibrate a transistor compact model and create two standard cell libraries, one for each temperature. We perform synthesis and physical layout of a RISC-V SoC at 300 K and analyze its performance at 10 K. Our simulations show that the SoC at 10 K is plausible but lacks the performance to process more than a few thousand qubits under the time constraint.
2023Published in IEEE Transactions on Quantum Engineering volume 4 on pages 1-11. 10.1109/TQE.2023.3300833