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A 0.4-1
  • Rakesh Verma Rena ,
  • Raviteja Kammari ,
  • Vijay Shankar Pasupureddi
Rakesh Verma Rena
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Raviteja Kammari
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Vijay Shankar Pasupureddi
Indian Institute of Technology Bhubaneswar

Corresponding Author:[email protected]

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Abstract

Abstract—Sub-sampling down-conversion has not been a popular choice for mixer-first RF front-ends for two interdependent reasons. One, the sub-sampling down conversion is inherently heterodyne in nature. Two, as a consequence to one, the passive mixer transparency property can not be exploited for providing impedance matching at the RF-port by impedance translation. In this work, an 8-path quarter-rate sub-sampling mixer-first direct down-conversion architecture is proposed to address these issues.  The proposed architecture simultaneously achieves quadrature direct down-conversion and impedance matching by using the third harmonic of the quarter-rate sub-sampling frequency, fs. The impedance matching is achieved by exploiting the 8-path passive mixer transparency property. Compared to RF sampling receivers, this architecture employs a sampling frequency fs three times lesser than fRF , saving on the power consumption of nonoverlapping clock generation, distribution circuits, and frequency synthesizer. To validate the proposed architecture, a test chip is fabricated in 1.2 V, 65 nm CMOS technology. The prototype occupies an active area of 0.32 mm2. The measurement results show that the sub-sampling 8-path mixer consumes a power of 800 μW, non-overlapping clock generation circuit consumes 2 to 9.2 mW, base-band LNA and gm-cell consume 26 mW over the frequency band 0.4-1.8 GHz with 90 MHz bandwidth. The receiver has a DSB noise figure of 4.7 dB, a conversion gain of 22 dB, an IB-IIP3 of -1 dBm and OB-IIP3 of +8 dBm.