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HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS in RISC-V Architectures
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  • nicasio canino ,
  • stefano di matteo ,
  • Daniele Rossi ,
  • Sergio Saponara
nicasio canino
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stefano di matteo
University of Pisa

Corresponding Author:[email protected]

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Daniele Rossi
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Sergio Saponara
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Peer review status:Published

2024Published in IEEE Access on pages 1-1. https://doi.org/10.1109/ACCESS.2024.3393844