A pulse stretching Time to Digital Converter (TDC) exploits the crosstalk effect on FPGA routing tracks is proposed. The principle idea is to superpose an induction voltage on the rising edge to lower its logic high toggling point while maintaining the falling edge intact. Thanks to the constant back induction voltage on the coupled transmission line, logic pulses can be stretched in a consistent manner.

The focus of this cross-talking TDC is to ameliorate the delay variations caused by temperature changes in conventional TDC designs. Theoretical analysis of temperature stabilities on pass-transistors, track buffers and metal wires is presented. Mathematical models are derived to compare their respective delay changes. Detailed calculations are performed using an α power law based transition delay model with device parameters extracted from both the 0.18µm TSMC process and the 22nm FinFET process according to previous articles. The impact of error accumulation on series connected transistor lines are emphasized, which is compared with the temperature response of an interconnect crosstalk, where only femtosecond scale impact is expected. Meanwhile, the resolution manipulation capability, the time synchronization design and a noise filtering circuit are discussed.

Experiments were conducted at different temperatures on commercial devices. During tests, the single shot precision, the effective resolution, and the non-linearity performance have all reached state-of-the-art. Noting that, 80fs resolution was observed. Most importantly, improvement on temperature stability is confirmed.