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An Ultra Fast Settling and Low Area Bit Synchronizer Architecture
  • Amitava Ghosh ,
  • Anindya S. Dhar
Amitava Ghosh
Institute of Engineering and Management

Corresponding Author:[email protected]

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Anindya S. Dhar
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The research is focussed on designing a bit synchronizer for wireless sensor node (WSN) applications and specifically Medical Implant Communications Service (MICS) band WSNs. The basic philosophy is that on receiving a 0-1 initial bit transition from the transmitter, the bit synchronizer is activated and it generates a strobe signal at bit time intervals from an initial latency. Two methods for latency calculation has been described. One is off-chip and another is on-chip. The bit synchronizer has ultra fast settling capability, ultra low power consumption and low silicon area. These requirements are a must for bit synchronizers in WSNs. A non-ideal model of a BFSK receiver has been designed in MATLAB and the bit synchronizer operation has been tested. Bit error ratio less than 10-3 has been obtained (WSNs have less stringent error ratios).