A Novel Techniques to Reduce the Test Data Volume and Test Time for
General Configurations by Embedded Deterministic Testing
Abstract
The main goal of Design for Testability (DFT) is to offer a way to test
each node in the design (Netlist) for different kinds of defects in the
chip. These nodes that are to be checked by using the intended number of
patterns, the more thoroughly the design has been tested. Every node in
the architecture must be visible(observable) and controlled for this to
be achievable. These two concepts may be thought of as the cornerstones
of DFT, which must be adhered to in order to get the most test coverage
with the fewest possible patterns. This work is applied in the field of
IC manufacturing before IC gets fabricated. The parameters like
multi-voltages and temperature of IC will be determined with the help of
Scan Insertion, ATPG pattern generation, EDT test compression and
simulation using mentor graphics tool. In this script we are mainly
concentrated on the compression process of the data volume and test time
by generating automatic test patterns according to it and simulatingÂ