Mathematical Modeling of Device Currents in Space-Vector Modulated Two-Level Three-Phase Voltage Source Inverter

Accurate calculation of losses incurred in the power electronic converter is particularly essential in selection of devices and optimal thermal design. This article attempts to devise device current expressions in a space vector modulated (SVM) voltage source inverter (VSI). Emphasis is laid on deriving the equations which facilitate for quick and accurate calculation of conduction losses in the converter at different load conditions. Importance of the proposed work also lies in providing a generic way of mathematical modeling of device currents in complex pulse-width modulation (PWM) schemes. Initially, device currents in SVM inverter without considering dead-time was presented, where a generalized expression for offset voltage is derived. As dead-time is absolutely essential for safe operation of devices, effect of dead-time consideration on device currents is discussed. Finally, as channel of mosfets can conduct bidirectionally, the device currents considering reverse conduction of mosfets is presented. Simulation analysis is performed using matlab/simulink. The effectiveness of the derived expressions is also validated experimentally using 415 V, 5 kW SiC mosfet based voltage source inverter setup.

selection of power devices and the design of thermal layouts.But, precise calculation and measurement of power losses in general is very tedious and arduous, owing to large number of non-idealities of a power electronic device.Power losses are broadly classified into conduction and switching losses.To calculate the switching losses, understanding of the energy losses during turn-on and turn-off transitions of the devices is essential.Different approaches like physics based models, numerical models, behavioural model, and analytical models are presented in the literature [6], [7], [8], [9], [10].The static characteristics like ON-state resistance and forward voltage drop of devices is essential for calculation of conduction losses in addition to the current flowing through the device [11], [12], [13], [14], [15], [16], [17].However, owing to complex switching schemes, the device current waveforms are quite complex to analyze.Thus, analytical calculation reduces the mathematical complexity and saves computational effort.This article emphasizes on presenting a methodology to devise the device currents in a reliable way.Although, the article deals with the formulation of device currents in space-vector PWM (SVM) inverter, similar methods can be employed to other modulation schemes.
In literature, evaluation of average and RMS current expressions for sine pulse width modulation (SPWM) was presented in [11] and for third-harmonic injected PWM (THIPWM), busclamping PWM was presented in [12], [13], [14].Essential idea employed in deriving device currents is, in any modulation scheme for voltage source inverter (VSI), phase current flows through the devices when they are switched-ON.It is claimed that SVM is similar to THIPWM, and device current expressions 0093-9994 © 2023 IEEE.Personal use is permitted, but republication/redistribution requires IEEE permission.
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obtained in THIPWM inverter can be directly applied to a SVM inverter [12], [13].But, the fundamental difference is the offset signal in both modulating schemes.The offset or the common mode voltage added in THIPWM inverter contains only third harmonic component of the fundamental frequency, whereas, in SVM inverter offset voltage added will contain all triplen harmonics.Owing to this, the modulating waves for SVM varies from THIPWM.Hence, derived closed-form expressions using THIPWM will have larger deviation when applied in a SVM inverter.The authors have presented device currents in SVM inverter, by formulating generalized expression for offset voltage, and compute device currents based on initial position of reference vector [18].However, dead-time was not considered in [11], [12], [13], [18], owing to which the derived expressions of device currents are not exact with respect to practical converters.Its consideration is essential for safe operation of VSI, as all practical switches are non-ideal and have non-zero rise and fall times.The influence of dead-time is presented in [19], [20], [21] does not explicitly study its influence on phase currents of inverter.
In the latter part of this article, it details the considerations required to formulate the device currents in a SVM inverter taking into account the reverse conduction of MOSFETs.When the gate of MOSFET is not biased beyond the threshold value, only the body diode of the MOSFET will conduct.However, when the gate pulse of sufficient magnitude is applied, then the channel is formed and thereby enabling the MOSFET to conduct in reverse direction (viz., source to drain).Owing to poor static characteristics of body diode of power MOSFETs, reverse conduction capability enables to obtain higher efficiencies and lower conduction losses [22], [23], [24], [25].
This article primarily aims to estimate the conduction losses by deriving precise closed-form solutions for device currents in an SVM inverter, specifically applicable to practical scenarios involving factors like deadtime and MOSFET reverse conduction.However, it does not account for non-idealities in static characteristics of power device.Unless explicitly mentioned, in the reminder of the article, the analysis presented is for a converter with a lagging load and the derived expressions currents correspond to the positive half cycle of phase current.Section II derives a generalized expression of offset voltage in SVM inverter, Section III computes device currents when dead-time is not considered.Section IV describes the effect of dead-time consideration in VSI.Section V computes device currents with dead-time consideration.Section VI presents analysis of device currents considering third quadrant conduction of MOSFETs.Section VII presents the validation of device currents calculated analytically, by simulation and experiments.Concluding remarks are provided in Section VIII.

II. GENERALIZED EXPRESSION OF OFFSET VOLTAGE
For a 2-level, 3-phase SVM inverter, there are 6-sectors, implying that offset voltage changes for every 60 • interval.Thus, to deduce device currents, it is necessary to formulate a generalized expression of offset voltage.Average and RMS device current given by ( 2), (3) are computed by multiplying the phase current with corresponding duty function and appropriately integrating over a fundamental period, where, theta (θ) is the reference angle of rotating vector, phi (φ) is the displacement power factor angle, I m is the maximum phase current, d dvc is the duty function of the device.Since, device currents for positive half-cycle of phase current are being derived, integration limits are considered to be (1) Theta (θ) belongs to fundamental period of sine function (viz.; . A generalized offset voltage (d of f ), defined as negated average of minimum (d min ) and maximum (d max ) duty function is obtained as shown in (6) [18].Modulating signals for top and bottom devices of SVM inverter result as shown in ( 7), ( 8) respectively.
where, d dvc,t,n , d dvc,b,n are the top and bottom device duty functions respectively.Note that (4) to (8) are function of sector (n), hence these expressions change for every π 3 interval of theta (θ).

III. COMPUTATION OF DEVICE CURRENTS WITHOUT DEAD-TIME CONSIDERATION
Incorporating phase current and modulating functions, average and RMS device currents are computed accordingly.
From space-vector shown in Fig. 2, it is seen that, based on the power-factor angle, the initial reference vector starts in either sector-5 or sector-6.The pink shaded area shows the region in which the reference vector traverses, viz., with reference to Fig. 2(a), it traverses in sectors 5, 6, 1, 2 and with reference to Fig. 2(b), it traverses in sectors 6, 1, 2, 3.
Owing to the cases mentioned above, it is essential to formulate device currents in two different cases.Performing the integrations given by ( 9), (10) shown at the bottom of the next page, average and RMS device currents for φ < π 6 result in (13), (14) and using the integrals given by (11), (12) shown at the bottom of this page, average and RMS device currents for φ > π 6 are shown in (15), ( 16) respectively.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.I dvc,avg where, for positive half cycle of load current, '±' denotes top and bottom device current expressions respectively (viz., to obtain top device current use '+' and for bottom device current use '−')

IV. EFFECT OF DEAD-TIME ON INVERTER
In Section III, the analysis presented does not consider blanking time.In this section, the device currents derived in the preceding section are modified to include the effect of blanking time.Dead-time refers to the time-interval between instant when a switch turns-OFF to the instant when its complementary switch turns-ON.Dead-time consideration is absolutely essential for safe operation of inverter owing to non-zero rise and fall times.By convention, phase current out of switching node, is considered to be positive and phase current into switching node, is considered to be negative.Dead-time consideration introduces an error in pole voltage and distorts load current in inverter.

A. Effect of Dead-Time on Inverter Pole Voltage
Effect of dead-time on inverter pole voltage (defined as voltage between switching node of a phase to the DC-midpoint) was presented in [20], [26], [27], which is briefly discussed in this sub-section, inferences of which will be used in subsequent sub-section.Two switching cycles in positive half-cycle of phase current are considered in Fig. 3.It shows comparison between carrier and modulating signal, ideal and actual gate pulses, ideal pole voltage, actual pole voltage and error in pole voltage due to delay in the pulses.
v p,id is the pole voltage obtained by considering ideal gate pulses shown as G 1,id , G 2,id .Actual gate pulses are obtained by introducing a delay or dead-time (t d ) at leading edge of ideal gate pulses, which result in gate pulses given as G 1,dy , G 2,dy .This causes a deviation in actual and ideal pole voltages, viz.; during dead-time interval, pulses for both switches are low, bottom diode conducts in this period, owing to phase current being positive.Hence, the pole voltage continues to be at 0.5 V dc potential, for an extra duration of t d .This introduces an error of V dc shown as v e defined by (17). (10) Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Since, dead-time is introduced at leading edge of pulses, the error voltage is seen where the conduction transitions from diode to switch.In positive half-cycle of phase current, ideal pole voltage is greater than actual pole voltage, which result in a train of instantaneous negative error voltage pulses and for negative half-cycle phase current, ideal pole voltage is lesser than actual pole voltage, which results in a train of instantaneous positive error voltage pulses as shown in Fig. 4.
Thus, error voltage depends upon the polarity of phase current.The average error voltage given by ( 18) is a square wave.The fundamental component of average dead time voltage is given by (19).
(v e,avg ) where, V dc is the DC bus voltage, t d is the dead-time, T sw is the switching time period, f sw is the switching frequency, sgn(i) is the polarity of phase current.

B. Effect of Dead-Time on Phase Current
By introduction of dead-time, ideal and actual pole voltage are not identical, which in-turn distorts the phase current.As explained, the polarity of error voltage changes with the change in polarity of actual phase current, thus, it is mandatory to compute the zero crossing of the actual phase current. where, To obtain the zero crossing of phase current, ( 20) is equated to zero, which results in (21).Fig. 5 shows sinusoidal and exponentially varying phase currents.Ideal sinusoidally varying phase current is given by (22).Since, load is considered to be lagging, the current response due to average error voltage will be exponential in nature.In steady-state, exponentially varying current ranges from I d,min to I d,max as shown in in Fig. 5. Solving for the current response of a square-wave excited RL circuit results in I d,max as given by (23).
where, τ is the time-constant of the circuit, which is equal to L/R, ΔV is the magnitude of average error voltage equal to V dc t d f sw .From Fig. 5, it is inferred that the actual phase current has a positive zero crossing at θ = φ dead .This implies that, at the zero crossing, ideal sinusoidal current given in ( 22) is equal to I d,max shown as (23), equating these equations eventually result as (24).
The fundamental quantities ideal pole and error voltages, actual phase current are as given by ( 25)- (27).

V. COMPUTATION OF DEVICE CURRENTS WITH DEAD-TIME CONSIDERATION
Effect of dead-time on pole voltage and phase current was imperative to formulate the device currents considering dead-time.For finding device currents, it is key to obtain valid modulating function as described in Section II.In this section, modified modulating function and device currents considering dead-time are articulated.

A. Modulating Function Considering Dead-Time
In Fig. 6, a reduction term (Δm) given by ( 29) is subtracted or added, to the ideal sinusoidal modulating signals (m sw , where Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply. where, V c,pk is the peak value of carrier wave.G  30), (31).
The device currents considering dead-time are to be analysed in two cases for the same reasons discussed in Section III.It is worth noting that, the two cases are with respect to the fundamental of actual current vector angle as shown in Fig. 7 (viz., ψ < π 6 and ψ > π 6 , where ψ is the positive zero crossing angle of fundamental of actual phase current).I dvc,rms = 1 2π By, appropriate substitution of ( 27), ( 30), ( 31) in ( 32), (33), device currents are obtained.Average and RMS device currents for ψ < π 6 shown as (34), ( 35) and for ψ > π 6 shown as (36), (37) are obtained. (35) where, for positive half cycle of load current, to obtain top device current equation use upper sign and for bottom device current use sign below.

VI. COMPUTATION OF DEVICE CURRENTS WITH REVERSE CONDUCTION OF MOSFET CHANNEL
The channel of a MOSFET possesses the capability to conduct current even when there is a negative drain-source voltage bias, provided the applied gate to source voltage is beyond the threshold voltage, V gs,th .In a half-bridge configuration, appropriate gate pulses and their complementary pulses are applied to the upper and lower MOSFETs.The conduction path for the phase current depends on factors such as the instantaneous value of the phase current, the static characteristics of the MOSFET channel and of the diode.
Based on circuit conditions, there are two possible scenarios: 1) Only MOSFET channel will conduct the phase current.
2) Alternatively, both the MOSFET channel and the diode will conduct the phase current.This behaviour of the MOSFETs presents a significant advantage in terms of reducing the conduction losses in the converter.In other words, the division of phase current between the diode and the MOSFET channel results in lower total conduction losses compared to the scenario where only the diode carries the entire phase current.Therefore, it plays a crucial role in enhancing overall efficiency and reducing thermal stress on devices in a power electronic converter.In Sections III and V, reverse conduction of MOSFETs was not considered.In this section, all cases arising due to reverse conduction of MOSFET and mathematical analysis to formulate device currents are detailed.Finally, the analysis is validated using a practical scenario, results are presented in Section VII.
Fig. 8(a) shows one leg of three phase VSI, where i ph is the phase current.Fig. 8(b) depicts the electrical circuit equivalent when both top MOSFET and diode are conducting in parallel.The parallel conduction of both the devices is only valid for the period where the diode is forward-biased (FB).The instant at which diode is FB is termed as reverse conduction angle (β), which is given by (38) [24], where V d is the forward-voltage drop of body diode, R on is the ON-state resistance of MOSFET and I m is the maximum phase current.
where, (44) The current flowing through the MOSFET, when only its channel is conducting is given by (39).Expressions (40), (41) describe the currents flowing through MOSFET and its body diode, during the period of parallel conduction.Thus, when parallel conduction is considered, average and RMS integration given by ( 2), (3) result as (42), (44) for MOSFET and (43), (45) for diode.As conduction losses in the devices will be a function of their respective device currents and static characteristics, therefore, it is essential to differentiate between the currents flowing through the diode and the MOSFET.The mathematical equations for calculating conduction losses of MOSFET and diode are shown as (46), (47) respectively.
It is re-iterated here that, the modulating function in the SVM changes for every π 3 interval of theta (θ).Hence, the position of the limits in the equations described above are to be determined, in order to properly divide into sub-integrals.Fig. 9 shows a valid range −β and φ.For (38) to have a valid solution the forward voltage drop of diode (V d ) must be in the range of [0, I m R on ].This implies that −β ∈ [−90 • , 0 • ] as shown by green shaded region in Fig. 9.The valid range of power factor (φ) is given by region shaded in pink.
The position of −β + φ, π + β + φ determine respectively the start and end sectors, and also determines the period when only channel conducts.Different combinations of angles β, φ give rise to different start and end sectors as shown in Fig. 10.For example, Fig. 10 It also shows a column named 'Integration number', which will be used to as reference in the integrations split described in reminder of the article.
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The final step in the articulation of the device currents is to split the integrals with appropriate limits based on the start and end sectors as described in Table I.For example, consider the case with integration number given as 1.a, to calculate the average currents flowing through the MOSFET and diode, the integration mentioned in (42), (43) are to be split as given by ( 48), (49) respectively.For calculating the RMS device currents, the sub-integrals remain the same, but the current has to be appropriately substituted.The final analytical expressions that account for reverse conduction can be intricate to derive due to the extensive number of variables involved.Hence, only the integration split is presented, depending on the numerical values for β and φ, the reader can use one of the eight cases described.This article does not cover the formulation of device currents in space vector modulated inverters that account for both dead-time and reverse conduction consideration.

VII. SIMULATION AND EXPERIMENTAL RESULTS
In this section, device current expressions formulated are validated.Expressions without dead-time consideration are validated only by simulation, whereas device currents equations with dead-time consideration are validated by simulation and experimental setup.Device current analysis when reverse conduction is accounted for is validated by taking a case scenario, where the data on non-idealities are obtained from datasheet of C2M0080120D manufactured by CREE.All simulation results presented in this section are performed using MATLAB/SIMULINK and hardware results are obtained by a 5 kW, 415 V 3-phase inverter setup.As seen in ( 13)-( 16) and ( 34)-( 37), the device currents are dependent on various parameters.Thus, in order to authenticate the device currents derived, each of these parameters are spanned over a wide range and the deviation of analytical values and simulation/experimental values are observed.

A. Results Without Dead-Time Consideration
Tables II and III compares normalized current values obtained from proposed and conventional analytical expressions with simulated results of SVM inverter for φ < π 6 , φ > π 6 respectively.The parameters influencing the device currents without dead-time consideration are power factor, modulation index and active power of load as shown in ( 13)- (16).Validation of the equations by varying each of the mentioned parameters are performed and exhaustive results were presented in [18].All the plots show that the analytical values obtained are in excellent co-relation with the simulated values.

B. Method for Device Current Measurement
The practical feasibility of directly measuring device currents using measuring tools such as current sensors or Rogowski coils is discussed in this particular sub-section.
Many designs which use power modules like B6, half-bridge module (for example, FM3, BM2 modules manufactured by CREE [28], [29], EasyDUAL manufactured by Infineon [30]), inhibits access to the points essential for direct measurement of device currents as they are internal to the package, rendering the practical placement of a current sensor infeasible.
Fig. 11(a) presents an illustrative model featuring a single half-bridge employing TO-247-3 packaged devices.To facilitate direct probing of device currents, a cut-out must be integrated into the PCB to accommodate the current sensor.Such a design, while enabling direct device current measurement, does not align favourably with other crucial metrics such as compactness, low power loop inductances, and is prone to a potential thermal stress in certain sections of the traces due to restricted current flow areas.In Fig. 11(b), a design using CAS120M12BM2 half-bridge power module is shown.In this configuration, the DC  bus-bar is positioned and connected directly over the terminals of the power device to minimize parasitic power loop inductance, this design does not allow for the integration of a current sensor due to spatial constraints.
Furthermore, the Rogowski coil is not suitable for direct measurement of device currents.This limitation arises from the frequency range of operation associated with the Rogowski coil.Specifically, the coil exhibits characteristics of reduced sensitivity at low frequencies, indicated by the "Droop factor" [31].This inherent characteristic of the coil introduces discrepancies between the actual waveform and the measured waveform.Fig. 12 displays an experimental result depicting the measurement of phase current (in red) using current probe and device current (in  blue) using a Rogowski coil.The specific Rogowski coil used in Fig. 12 employed in the experiment is identified by the part number TRCP0300 manufactured by Tektronix.It is designed with a frequency range of operation spanning from 9 Hz to 30 MHz, offering a sensitivity of 20 mV/A.Upon observation, it can be inferred that the Rogowski coil not only exhibits the droop characteristic but also introduces a phase-shift in the measured waveforms, which makes Rogowski coil an inappropriate choice for device current measurements.
In this paper, the approach employed for determining device currents involves the multiplication of phase current with the gate pulses of corresponding phase.This methodology is based on the concept that devices conduct phase current while in their ON-state.This forms the basis of proposed approach, making the method relatively simpler to obtain device currents.Therefore, this approach for measurements addresses the constraints associated with the measurement equipment discussed in this sub-section.In addition, the notable advantage of the proposed method is its capability to overcome the bandwidth limitations associated with direct measurement of device currents.However, it is to be noted that the device currents obtained can only be used to calculation conduction losses and is not applicable for the explicit purpose of estimating the switching losses in the converter.

C. Results With Dead-Time Consideration
Fig. 13-14 shows the hardware setup, probing points and assembled setup used to validate the equations.An SiC MOSFET C2M0080120D rated at 1200 V and 36 A is used as switch in the three-phase inverter [32].The details of the hardware components are provided in Table IV.The implementation of a space-vector modulation scheme was carried out using the TMS320F28377D micro-controller.During the experiments, phase current and gate-source voltage are probed as shown in Fig. 13.The following instruments are employed to conduct these measurements: 1) Gate-source voltage (V gs ): Differential probe, P5200 A with a bandwidth of 50 MHz.2) Phase current: Current probe, TCP0030 A with a bandwidth of 120 MHz. 3) Oscilloscope: Digital oscilloscope, Tektronix MDO3024 with a bandwidth of 200 MHz.The phase current and gate voltage data as shown in Fig. 15 is processed in MATLAB to remove any high frequency noise in the phase current waveform captured.Gate pulse voltage below and above threshold value is set to '0' and '1' respectively.The processed gate pulses and complementary pulses are multiplied with the filtered phase current to obtain the device currents.Device currents in positive half-cycle of the load current are as shown in Fig. 16.
Tables V and VI shows the deviation of analytical values with respect to simulated and experimental results obtained for ψ < π 6 , active power load of 1.6 kW and ψ > π 6 , active power load of 2.3 kW respectively.Other circuit conditions, namely V dc = 625 V, switching frequency (f sw ) = 10 kHz and dead-time (t d ) = 800 ns remain same for both cases.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.r Power factor is varied approximately from 0.35 to 0.95, at modulation index of 1.05, f sw of 10 kHz and dead-time of 800 ns.To vary the power factor, inductance of R-L load is kept constant at 61 mH and resistance is varied from 8.8 Ω to 60 Ω.At higher values load resistance, power factor is higher and vice-versa.r For ψ < π 6 , modulation index is varied from 0.2 to 1.1, for load with R = 60 Ω and L = 61 mH.And ψ > π 6 , modulation index is varied from 0.1 to 1.1, for load with R = 25 Ω and L = 61 mH.In both cases, f sw is 10 kHz, dead-time is 800 ns.r For ψ < π 6 , active power load is varied from approximately 500 W to 2.5 kW, for load with R = 60 Ω and L = 61 mH and for ψ > π 6 , active power load is varied from approximately 450 W to 3.5 kW, for load with R = 25 Ω and L = 61 mH.In both cases, f sw is 10 kHz, dead-time is 800 ns.r Dead-time is varied from 500 ns to 1 μs, at f sw of 10 kHz.
Switching frequency is varied from 10 kHz to 40 kHz, at dead-time of 800 ns.In both cases, modulation is equal to 1.05, load of R = 25 Ω, L = 61 mH.Figs.17-19 show the deviation or error in the values obtained from the proposed expressions and the values obtained from simulation and experiments at different circuit parameter conditions respectively.It is observed that the deviation of analytical and simulated value is negligible over wide variation of all circuit parameters.However, the deviation of analytical and experimental values is slightly higher.Although, this is predominantly observed when the device currents are low.Owing to low value, a slight variation in the values lead to a greater deviation.

D. Results With Reverse Conduction of MOSFET
In this section, numerical calculations performed in MAT- LAB/SIMULINK to validate the expressions with reverse conduction of MOSFET is presented.A discrete MOSFET switch rated for 1200 V and 36 A, with part number C2M0080120D manufactured by CREE is used for analysis [32].The circuit parameters used for simulation are as follows: R on = 170 mΩ, V d = 2.5 V, R d = 80 mΩ, power factor angle of load (φ) = 20 • .
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.From the circuit parameters mentioned above, reverse conduction angle (β) is found to be 29.354• .Hence, only MOSFET channel will conduct for the period [−9.354 • , 229.354 • ], which corresponds to case 5.a as described in Table I.Analytical values and simulation results are shown in Table VII.
The MOSFET channel and the body diode are both internal to the packaging, making it infeasible to probe the device currents flowing through them discretely.Any alternate MOSFET configurations with external diodes are not considered.Fig. 20(a) shows an external Schottky diode connected in anti-parallel to the MOSFET.While Schottky diodes exhibit superior on-state characteristics compared to the body diode of power MOSFETs, this configuration would result in the phase current having three potential paths to split instead of two.However, the analysis in the article assumes that the phase current splits in only two paths, viz., between the body diode and the MOSFET.Configuration  in Fig. 20(b) does not allow for the reverse conduction of the MOSFET channel.Some works in literature on SPWM and THIPWM inverters [24], [25] with reverse conduction consideration of MOSFET uses calorimetric setup in order to validate the analytical expressions derived experimentally.However, such sophisticated setup to measure conduction losses is beyond the scope of this article.
In summary, the proposed equations provide highly accurate device current estimation for a space-vector modulated inverter, improving conduction power loss estimation.Despite uncertainties in static characteristics of devices, these equations are more accurate than the existing analytical expressions.They also enable for parametric studies under different conditions with minimal computational effort.While the expressions are specifically designed to cater to a two-level space vector modulated three-phase inverter, the approach can be extended to various modulation techniques, broadening its applicability for wide range of inverter configurations.

VIII. CONCLUSION
The article introduces closed-form expressions for device currents in a two-level three-phase space vector PWM modulated inverter.The proposed analysis formulates a generalized offset voltage equation, facilitating a clear understanding of the effective modulation function in each sector.The analysis further extends to encompass cases involving dead-time, reverse conduction of MOSFETs, making the proposed equations more accurate for real-life scenarios.Despite presenting various cases and sub-cases, the proposed method enables to visualize and comprehend these cases effortlessly, which aids in simplifying the complex integrations involved.
Validation of these expressions is done by simulation and as well as a 3-phase VSI hardware setup.In the analysis performed, several parameters influencing the proposed equations are varied over a wide range and deviation of values obtained analytically, by simulation and by experiment are studied.

Fig. 1 .
Fig. 1.Flowchart depicting the influence of power loss calculation on power device selection and thermal layout design in a power electronic converter.

Fig. 4 .
Fig. 4. (a) Error voltage due to dead-time consideration over a fundamental cycle of VSI operation and (b) fundamental of average error voltage.

Fig. 6 .
Fig. 6.Ideal, actual, and modified gate pulses obtained by comparison of modulating signal with high frequency carrier wave.

Fig. 8 .
Fig. 8. (a) One inverter leg of three-phase inverter, (b) equivalent circuit during simultaneous conduction of MOSFET and diode during negative half of phase current, and (c) parallel conduction device currents waveform.
(a) shows a space vector diagram for the case where β ∈ [0 • , 30 • ] and φ ∈ [0 • , 30 • ].The start sector defined by −β + φ ∈ [−30 • , 30 • ], implying that the start sector lies in 5th sector as shown by pink shaded region.The end sector given by π + β + φ ∈ [180 • , 240 • ], implying that end sector lies in either 2nd or 3rd sector as shown by green shaded region.Similar colour coded regions are depicted for other conditions.From Fig. 10, Table I is tabulated, which details a complete chart of all possible cases and sub-cases showing start and end sectors.

Fig. 11 .
Fig. 11.Picture showing (a) a representational model with a cutout in PCB for direct measurement of device current and (b) placement of Rogowski coil in inverter setup with BM2 power modules manufactured by CREE.

Fig. 12 .
Fig. 12. Plot showing the measurement of phase current using current probe and device currents using TRCP0300 Rogowski coil.

Fig. 13 .
Fig. 13.Hardware setup of 5 kW, 415 V three phase inverter and corresponding schematic showing probing points.

Fig. 16 .
Fig. 16.Plot showing top and bottom device currents in positive half-cycle of load current obtained by multiplication of phase current and gate pulses.

TABLE I START
AND END SECTORS: ONLY CHANNEL CONDUCTION OF MOSFET

TABLE II DEVIATION
INNORMALIZED DEVICE CURRENTS OF PROPOSED AND CONVENTIONAL EXPRESSIONS FOR φ < π 6 W/O DEAD-TIME CONSIDERATION TABLE III DEVIATION IN NORMALIZED DEVICE CURRENTS OF PROPOSED AND CONVENTIONAL EXPRESSIONS FOR φ > π 6 W/O DEAD-TIME CONSIDERATION

TABLE IV PARAMETER
AND COMPONENT SELECTION OF VSI

TABLE V DEVIATION
OF ANALYTICAL VALUES WITH RESPECT TO SIMULATED AND EXPERIMENTAL VALUES FOR ψ < π 6 WITH DEAD-TIME CONSIDERATION TABLE VI DEVIATION OF ANALYTICAL VALUES WITH RESPECT TO SIMULATED AND EXPERIMENTAL VALUES FOR ψ > π 6 WITH DEAD-TIME CONSIDERATION

TABLE VII DEVIATION
INDEVICE CURRENTS WITH REVERSE CONDUCTION