Approximate circuit design has gained significance in recent years
targeting error tolerant applications. In this paper, we consider the
problem of minimizing the power for a given

accuracy, in a signal processing application with accurate adders
replaced by low-power approximate adders. We first demonstrate that the
commonly used assumption that the inputs to the adder are uniformly
distributed results in an inaccurate prediction of error statistics for
multi-level circuits. To overcome this problem, we propose the use of
parameterized error models for adders, with input static probabilities
as parameters. The static probability computation in our work considers
not just the functionality of the adder but also its position in the
circuit, functionality of its parents and the number of approximate bits
in the parent blocks. This parameterized error model can be incorporated
in any optimization framework. We demonstrate up to 6.5 dB improvement
in the accuracy of noise power prediction when the proposed model is
used to optimize an 8x8 DCT.