Abstract

We present an oscillator design based on stacked-FET for high power terahertz signal generation in CMOS technologies. This design addresses the challenges commonly encountered in conventional high-power oscillators. These challenges include low inductor quality factor (Q) associated with the use of large active devices, and the need for extensive chip area when combining multiple optimally-designed cells. Based on a Π-embedded oscillator architecture, we show that, with N-stacked FET, the optimal embedding inductor and load resistance increase approximately with N. This contrasts with the traditional size scaling approach, where L and R decreases unfavorably as the device size increases. We take advantage of this characteristic, by proposing a design methodology that simultaneously achieves high output power and optimal inductor Q. The concept is validated by a design example of a two-stacked Π-embedded oscillator operating at 180 GHz and fabricated in 45-nm CMOS SOI, delivering 11 dBm RF power from two losslessly combined oscillator cores. This design demonstrates the highest output power among CMOS oscillators at this frequency.