<div>This paper presents the first experimental demonstration</div>


<div>of a ternary memristor-CMOS logic family. We systematically</div>


<div>design, simulate and experimentally verify the primitive</div>


<div>logic functions: the ternary AND, OR and NOT gates. These are then used
to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as
data handling ternary MAX and MIN gates. Our simulations are performed
using a 50-nm process which are verified with in-house fabricated
indium-tin-oxide memristors, optimized for fast switching, high
transconductance, and low current leakage. We obtain close to an order
of magnitude improvement in data density over conventional CMOS logic,
and a reduction of switching speed by a factor of 13 over prior
state-of-the-art ternary memristor results. We anticipate extensions of
this work can realize practical implementation where high data density
is of critical importance.</div>