Fast Hierarchical Optimization Method for High Speed Channel Design
Using Channel Operating Margin
Abstract
This paper proposes a design flow for channel design by a fast
hierarchical optimization method based on Channel Operating Margin
(COM). Unlike the common design of experiment (DOE), the method performs
the design by a hierarchical flow in the level of electrical
characteristic while not the usual horizontal structure of physical
parameters. It significantly reduces the number of huge samples used in
DOE, and thus is able to offer a fast estimation approach for channel in
the early design period. In each stage of the vertical flow, the
electrical properties of component are extracted by 2.5D or 3D full wave
simulator, and thus ensure the accuracy of the channel design. Design
strategy for the most crucial discontinuity, Via, to achieve an
impedance matching is addressed. Package effect on the COM is also
discussed as a reference for adjusting the 3dB criterion of COM in the
future.