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A Novel Low-Power Encryption Scheme Based on Chaotic Dynamic Triple Pendulum System for Wide Range of Applications
  • Bikram Paul
Bikram Paul
Indian Institute of Technology Guwahati

Corresponding Author:[email protected]

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Recent advancements in the domain of quantum computing are posing a security threat to the classical cryptography algorithms. Popular symmetric and asymmetric cryptosystems including RSA, ECC, DES, Diffie-Hellman etc. can be broken by a quantum computer executing Shors and Grovers algorithms. This motivated scientific community to design newer encryption schemes to address security vulnerabilities. Hash, Code, Lattice, Multivariate Polynomial based cryptography algorithms, known as post-quantum cryptography algorithms (PQC), exhibit resistance against classical as well as quantum crypto-attacks. Apart from these PQC algorithms, a relatively new method of constructing cryptosystems utilizing the unpredictability property of discrete chaotic dynamic systems has become noteworthy from the practical perspective. In this paper, we present a novel approach to design an encryption scheme based on the chaotic dynamic physical system, which is derived from a mechanical model depicting nonlinear dynamics and exhibits resistance against various attacks. The effectiveness of the proposed cryptography scheme is validated against various standard tests, such as Lyapunov exponents test, bifurcation diagrams, sensitivity to parametric and to initial values, ergodicity, collision test, NIST, diehard randomness test etc. This algorithm is also verified through an FPGA implementation to assess its usage in low power high throughput applications as well. The power consumption and resource utilization of the proposed design are 56 % and 72.6 %, respectively, as compared to other known methods while operating at 628.14 MHz. It is observed that the proposed design can work efficiently with various wide range of applications. It is observed that the proposed design can work efficiently with various wide range of applications. The average power and area of its ASIC implementation at 180 nm technology are 61.8836 mW and 0.20374 mm 2 at 250 MHz, respectively.