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DE Stack on Performance of NCFET
  • Harshit Kansal ,
  • Aditya S Medury
Harshit Kansal
Indian Institute of Science Education and Research Bhopal

Corresponding Author:[email protected]

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Aditya S Medury
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Abstract

In this letter, through TCAD simulations, we show that the introduction of a thin paraelectric (PE) layer between the ferroelectric (FE) and dielectric (DE) layers in an MFIS structure, expands the design space for the FE layer enabling hysteresis-free and steep subthreshold behavior, even with a thicker FE layer. This can be explained by analyzing the FE-PE stack from a capacitance perspective where the thickness of the PE layer in the FE-PE stack has the effect of reducing the FE layer thickness, while also reducing the remnant polarization. Finally, for the same FE-PE-DE stack, analog performance parameters such as $\frac{g_{m}} g_{ds}}$ and $\frac{g_{m}}{I_{d}}$ are analyzed, showing good characteristics over a wide range of gate lengths, at low drain voltages, thus demonstrating applicability for low power applications.
07 Oct 2022Published in Silicon. 10.1007/s12633-022-02054-2