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Design of High-Speed Multiway Merge Sorting Networks Using Fast Single-Stage N-Sorters and N-Filters
  • Robert Kent ,
  • Marios Pattichis
Robert Kent
University of New Mexico

Corresponding Author:[email protected]

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Marios Pattichis
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In hardware such as FPGAs, Kenneth Batcher’s Odd-Even Merge Sort and Bitonic Merge Sort are the
state-of-the-art methodologies used to quickly sort a list of more than 16 input values. Both sorting networks
feature merges of 2 sorted input lists into a single sorted output list. For both, a full sort of 64 and 512
input values requires 21 and 45 serial stages, respectively. Multiway merge sorting networks described here
require significantly fewer serial stages. For example, 8-way merge networks fully sort 64 and 512 input
values in 9 and 20 serial stages, less than half the number of the respective 2-way networks. When the
multiway merge sorting networks utilize the single-stage N-sorters recently defined by the authors, they are
considerably faster than Batcher’s networks. In the AMD-Xilinx Ultrascale+ xcvu9p FPGA, the two 8-way
merge networks have speedups of 1.85 and 1.74 versus the comparable 2-way networks. A fully pipelined
3-way merge network in this FPGA is capable of fully sorting 500 million lists of 729 unsorted 32-bit
values in one second. In software, multiway merge methods are used to find the median of certain pixel
rectangles in images, since the median can be determined in fewer stages than are required to fully sort the
rectangle. However, the software still requires a series of many 2-sorter operations to find a median. These
multiway merge median methods are dramatically sped up in hardware, where the authors’ new single-stage
N-sorters and N-filters operate in parallel in each stage of the merge process.
2022Published in IEEE Access volume 10 on pages 77980-77992. 10.1109/ACCESS.2022.3193370