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Flip Chip Bonding for SiC Integrated Circuits with Gold Stud Bumps for High Temperature (Up to 600°C) Applications
  • Feng Li
Feng Li
University of Idaho

Corresponding Author:[email protected]

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This work studies the 3D stacking of an approach to silicon carbide (SiC) integrated circuit (IC) chips using flip-chip technology with gold stud bumps for high-temperature (up to 600°C) applications. Standard photolithography, sputtering deposition, and lift-off process were used for chip metallization and patterning with titanium (Ti), tantalum silicide (TaSi2), platinum (Pt), and gold (Au) thin films. Gold stud bumps were used to bond the SiC chips with a flip-chip die bonder forming a daisy chain connection. Die shear tests were conducted, and the electric resistance of the daisy chain interconnect between the chips was measured before and after thermal aging in the air at 600°C for up to twelve days. It is found that the electric resistance of the daisy chain interconnects decreases with heating and stabilizes at about 1 Ohm for 36 bumps, showing that the thermal aging process improves the electric performance of the interconnect with gold stud bumps. The destructive die shear test shows that, with thermal aging, the shear force decreases for the chip stacks and stabilizes at about 15-gram force (gf) per bump with TaSi2 diffusion barrier in the metallization. In contrast, the shear strength increases for the chip stacks without TaSi2 barrier in the metallization.