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First Demonstration of Reconfigurable Threshold Logic Gate using FeFET
  • +2
  • Shubham Kumar,
  • Gian Singh,
  • Sarma Vrudhula,
  • Yogesh Singh Chauhan,
  • Hussam Amrouch
Shubham Kumar

Corresponding Author:[email protected]

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Gian Singh
Sarma Vrudhula
Yogesh Singh Chauhan
Hussam Amrouch

Abstract

This study introduces the first-of-its-kind Reconfigurable Threshold Logic Gate (R-TLG) using Ferroelectric FET (FeFET) devices. The experimental measurements of 28 nm FeFETs demonstrate that four distinct threshold voltage (V TH) states can be reliably programmed in presence of variation. We employ such multilevel FeFETs to implement a novel R-TLG in which the weights of the threshold functions are encoded within the four different analog states of FeFETs. Our R-TLG consists of merely 26 transistors, which is less than the number of transistors in a single D-FF gate, yet it is capable to realize 13 different complex Boolean functions. The total number of transistors to realize those functions in convectional CMOS reaches 220, which is 8.5x higher than what our FeFET-based R-TLG requires. This translates into a remarkable area saving, which is very crucial in an era where computational demands incessantly escalate due to AI applications. Further, the variety of Boolean functions that our R-TLG realizes not only optimizes area, but also bolsters IP security through camouflaging because thieves must navigate a much larger design space while reverse engineering.
23 Jan 2024Submitted to TechRxiv
26 Jan 2024Published in TechRxiv