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A Novel Algorithm for Transforming S-Parameters to Reduced-Order Passivity-Enforced Equivalent Circuit (SROPEE)
  • Rasul Choupanzadeh,
  • Ata Zadehgol
Rasul Choupanzadeh

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Ata Zadehgol
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Abstract

This paper presents SRPOEE which is a novel algorithm and automated Python-based open-source software (OSS) designed to synthesize the reduced-order passivity-enforced equivalent circuits of networks represented by scattering parameters (S-parameters). The proposed algorithm comprises three main modules Full Synthesis, Passive MOR, and Reduced Synthesis, each incorporating a combination of established and novel techniques. The Full synthesis module calculates a fullorder passive fitted system in state-space form, via fitting the given S-parameters using the vector fitting (VF) method, and assesses/enforces passivity through the singularity half-size test matrix method. Subsequently, it synthesizes a full-order equivalent circuit, comprised of R/L/C circuit elements, based on the calculated full-order fitted system. The Passive MOR module represents the synthesized full-order equivalent circuits using modified nodal analysis (MNA) matrices, and subsequently reduces the order of these matrices through a model order reduction (MOR) technique known as the Block SAPOR technique. Finally, the Reduced Synthesis module constructs a reduced-order equivalent circuit composed of R/L/C circuit elements based on the reduced-order MNA matrices generated in the previous module. In addition to synthesizing the reduced-and full-order equivalent circuits, SROPEE also generates SPICE-compatible netlists for both the full-and reduced-order equivalent circuits, enabling further circuit analysis in SPICE circuit solvers. We evaluate SROPEE by comparing the network parameters of the synthesized reduced-order equivalent circuit with the original network parameters for a 4-port optical network operating in frequency range of 175-215 THz. Furthermore, we compare the computational costs of circuit analysis for synthesized fulland reduced-order equivalent circuits in terms of network order, matrix dimensions, compute-time, accuracy, memory utilization, and passivity considerations. The Python-based OSS may be deployed as a stand-alone tool, or integrated into existing process technology flows and CAD tools to expedite design automation.
20 Mar 2024Submitted to TechRxiv
29 Mar 2024Published in TechRxiv