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s 7-bit Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22nm FinFET
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  • Yuanming Zhu ,
  • Tong Liu ,
  • Srujan Kumar Kaile ,
  • Shiva Kiran ,
  • Il-Min Yi ,
  • Ruida Liu ,
  • Julian Camilo Gomez Diaz ,
  • Sebastian Hoyos ,
  • Samuel Palermo
Yuanming Zhu
Texas A&M University

Corresponding Author:[email protected]

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Srujan Kumar Kaile
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Shiva Kiran
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Il-Min Yi
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Ruida Liu
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Julian Camilo Gomez Diaz
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Sebastian Hoyos
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Samuel Palermo
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Efficient time-interleaved analog-to-digital converters (ADCs) that operate at high sample rates with wide input bandwidths are necessary to support increasing wireline transceiver data rates. This paper presents a 7-bit 38GS/s 32-way time-interleaved ADC that utilizes an 8-way interleaver architecture based on a speed-enhanced bootstrapped switch that increases input bandwidth. ADC sample rate and efficiency is improved with pipelined successive approximation register (SAR) unit ADCs that employ an output level shifting (OLS) settling technique in the dynamic residue amplifier to achieve settling in only 33% of the time required for a conventional current-mode logic (CML) amplifier. Using parallel comparators in the two 4-bit asynchronous pipeline stages allows for further improvements in ADC conversion speed. Fabricated in 22nm FinFET, the proposed ADC occupies 0.107mm2 area. Operating at 38GS/s, the ADC achieves 41.9fJ/conv.-step with low input frequencies, 64.1fJ/conv.-step at Nyquist, and has 20GHz 3dB input bandwidth.