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Design of Variation-Tolerant 1F-1T Memory Array for Neuromorphic Computing
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  • Masud S K Rana ,
  • Sunanda Thunder ,
  • Franz Müller ,
  • Nellie Laleni ,
  • Yannick Raffel ,
  • Maximilian Lederer ,
  • Luca Pirro ,
  • Talha Chohan ,
  • Jing-Hua Hsuen ,
  • Tian-Li Wu ,
  • Konrad Seidel ,
  • Thomas Kaempfe ,
  • Sourav De ,
  • Bhaswar Chakrabarti
Masud S K Rana
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Sunanda Thunder
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Franz Müller
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Nellie Laleni
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Yannick Raffel
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Maximilian Lederer
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Luca Pirro
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Talha Chohan
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Jing-Hua Hsuen
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Tian-Li Wu
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Konrad Seidel
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Thomas Kaempfe
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Sourav De
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Bhaswar Chakrabarti
Indian Institute of Technology Madras

Corresponding Author:[email protected]

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This letter proposes a memory cell, denoted by 1F-1T, consisting of a ferroelectric field-effect transistor (Fe-FET) cascoded with another current-limiting transistor (T). The transistor reduces the impact of drain current (Id) variations by limiting the on-state current in FeFET, denoted by 1F. We have fabricated 28nm high-k-meta-gate (HKMG) based FeFETs, and the experimental data is used to model and simulate single-cell and memory arrays. The simulation shows significant improvement in bit-line (BL) current (IBL ) variation for 1F-1T memory array. Finally, the system-level neuromorphic simulation with 1F-1T synapses shows an inference accuracy of 97.6% for MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.