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Efficient Automation of Memory Model Development Workflow: Streamlining the Design and Optimization Process
  • Tanmay Sinha ,
  • Dr. M Govinda Raju
Tanmay Sinha
RV College of Engineering

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Dr. M Govinda Raju
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In this paper, a new workflow of memory model front-end verification is explained with parallel execution of steps needed in between. This new flow involves the usage of multiprocess that are run parallely instead of sequential running which reduces the enormous amount of time required for the verification. Apart from this, the paper explains about the steps taken to enhance the modularity in order to enhance the readability of the script and utilizing it to get maximum output and efficiency. It is observed that the new design reduces the CPU time by 76% which is quite a lot for the verification point of view. Further, comparative study is performed for coverage report of unused test cases of the memory model thereby handling the negative test cases and it is concluded that all the positive and negative test cases are handled successfully in this new design workflow. Apart from this, variations in different versions is also tabulated with tradeoffs.