CMOS-based computing promises drastic improvement in performance in the cryogenic environment. The field of CMOS cryogenic environment-based computing holds the promise of delivering remarkable enhancements in both performance and power consumption. This is important to enable Quantum computing that holds great opportunity to achieve order of magnitude improvements in performance over traditional CMOS computing. Among the pivotal components enabling this advancement, Static Random-Access Memory (SRAM) stands as an indispensable element characterized by its superior performance and density. This contribution aims to develop a framework for examining the influence of leakage current, parasitic effects of bit-line and word-line, and voltage on the size and performance of the SRAM array under cryogenic temperatures. To accomplish this, we conducted simulations on the SRAM array, varying the number of rows and columns. For a comprehensive analysis, we further investigated the maximum attainable array size, extending our study to 10 K, utilizing three distinct cell types. Our findings substantiate the affirmative impact of cryogenic temperatures on both array size and performance. Additionally, we elucidate the influence of transistor threshold voltage engineering on the optimization of the SRAM array. A detailed spice simulation using measured data in the cryogenic environment using 5 nm FinFET is used. This work contributes a significant step forward in understanding and leveraging cryogenic technology.
The rise in quantum-computing systems, space electronics, and superconducting processors requires compatible cryogenic memories. The stringent operating conditions for these applications put additional constraints on the endurance and reliable operation of such memories. Ferroelectric-Field Effect Transistors (FeFETs) based on ferroelectric properties of the Hafnium Zirconium Oxide (HZO) can be an excellent choice for these systems. This requires a thorough characterization of FeFET at deep cryogenic temperatures. Also, the scalability of the FeFET to lower technology nodes implies a lower area and reduced leakage. In this work, we, therefore, fully characterize the 5 nm node Fe-FinFET from 10 K to 400 K. To this end, the underlying 5 nm node FinFET transistor is calibrated with experimental data from cryogenic temperatures to above-room temperatures. The material parameters of the Ferroelectric layer are also calibrated with reported measurement data. We propose that the reported endurance improvement of the HZO layer at cryogenic temperatures can improve the reliability of the Fe-FinFET. The observed wake-up and fatigue at higher temperatures are also non-existent at cryogenic temperatures. Although the memory window is reduced at cryogenic temperature compared to room temperature, we can still hold multiple states. This is also verified through our simulations. Lastly, we demonstrate the variability in high and low threshold voltage states due to extrinsic variation sources of the underlying transistor and ferroelectric material parameters. We observe a relatively lower variation at cryogenic temperature.