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Unveiling Enhanced Trade-offs in SRAM-based Memory Arrays for Cryogenic CMOS Technology
  • +2
  • Shivendra Singh Parihar,
  • Girish Pahwa,
  • Baker Mohammad,
  • Yogesh Singh Chauhan,
  • Hussam Amrouch
Shivendra Singh Parihar
Department of Electrical Engineering, Indian Institute of Technology Kanpur, University of Stuttgart

Corresponding Author:[email protected]

Author Profile
Girish Pahwa
Department of Electrical Engineering and Com-puter Sciences, University of California
Baker Mohammad
Department of Electrical Engineering and Computer Science, System on Chip Center, Khalifa University
Yogesh Singh Chauhan
Department of Electrical Engineering, Indian Institute of Technology Kanpur
Hussam Amrouch
Chair of AI Processor Design, Munich Institute of Robotics and Machine Intelligence (MIRMI), Technical University of Munich (TUM)


CMOS-based computing promises drastic improvement in performance in the cryogenic environment. The field of CMOS cryogenic environment-based computing holds the promise of delivering remarkable enhancements in both performance and power consumption. This is important to enable Quantum computing that holds great opportunity to achieve order of magnitude improvements in performance over traditional CMOS computing. Among the pivotal components enabling this advancement, Static Random-Access Memory (SRAM) stands as an indispensable element characterized by its superior performance and density. This contribution aims to develop a framework for examining the influence of leakage current, parasitic effects of bit-line and word-line, and voltage on the size and performance of the SRAM array under cryogenic temperatures. To accomplish this, we conducted simulations on the SRAM array, varying the number of rows and columns. For a comprehensive analysis, we further investigated the maximum attainable array size, extending our study to 10 K, utilizing three distinct cell types. Our findings substantiate the affirmative impact of cryogenic temperatures on both array size and performance. Additionally, we elucidate the influence of transistor threshold voltage engineering on the optimization of the SRAM array. A detailed spice simulation using measured data in the cryogenic environment using 5 nm FinFET is used. This work contributes a significant step forward in understanding and leveraging cryogenic technology.
15 Jan 2024Submitted to TechRxiv
26 Jan 2024Published in TechRxiv