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Improving the computational efficiency of lock-in algorithms through coherent averaging
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  • Matias Javier Oliva ,
  • Pablo Andrés García ,
  • Enrique Spinelli ,
  • Alejandro Luis Veiga
Matias Javier Oliva
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Pablo Andrés García
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Enrique Spinelli
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Alejandro Luis Veiga
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The lock-in amplifier is a commonly used technique for the processing of noisy signals with a known periodicity that involves multiplying the signal with one or more reference signals of the same periodicity and low-pass filtering the results. This enables the recovery of the amplitude and phase of the signal being measured. Another well studied technique to reduce the noise of periodic signals is the coherent averaging method, where the samples of a noisy signal with a known periodicity are averaged coherently. In this paper, a novel system combining both algorithms is proposed. In this approach, the signal is first averaged coherently for a number of cycles (Nca) and then passed through a conventional lock-in with a moving average filter of a whole number of periods of the signal (Nma) as a lowpass filter. In this scenario, the question of how to distribute the incoming samples between the coherent average and the conventional lock-in scheme arises. The mathematical aspects of this issue were evaluated, leading to the conclusion that the calculation results remain identical as long as the product NcaNma remains constant. However, it was observed that the number of operations required for each algorithm varies. By maximizing the number of samples used for the coherent average, the number of multiplications involved can be drastically reduced from NcaNmaM to just M, where M represents the number of samples in a single period of the signal. The drawbacks are the need for space to store the averaged signal, a slower convergence to the result, and an extra cycle in the calculations. Any lockin system with moving average filter can take advantage of these results. Particularly in this study, they are employed to nearly double the achievable clock frequency of a lock-in system implemented on a Cyclone V FPGA, taking it from 119.39 MHz to 216.54 MHz without the use of hardware embedded multipliers.