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Verification of Error Correction Codes for CPU Memories
  • Keerthana Ramesh ,
  • Shwetha Baliga
Keerthana Ramesh
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Shwetha Baliga
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This paper presents a strategy for the verification of error correction capability of SRAM memories in the CPU. The Error correction code used is a (72, 64) SEC-DED code that is capable of detecting 2 bit errors and correcting 1 bit errors in the memory. The strategy uses multiplexers to inject controlled bit flips into the memory only during verification. The RTL code for the ECC encoder and Decoder modules in written and the functional verification of ECC is performed using the error injection infrastructure that is built. Coverpoints are coded for various scenarios of error injection. These include controls for error injection in data bits or ECC bits, read path and write paths of the memory. Infrastructure is developed for single bit, multi- bit or a combination of both to be injected in a controlled fashion into the memory. This infrastructure is highly scalable to large memories as well. The infrastructure is completely synthesizable and hence suitable even for emulation.