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FPGA based Artificial Neural Network Processor for Detection of Epileptic Seizure
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  • Bharat Gupta ,
  • Yashwant Kumar Balivada ,
  • Mustafa Sameer ,
  • sanchita ghosh
Bharat Gupta
National Institute of Technology Patna, National Institute of Technology Patna

Corresponding Author:[email protected]

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Yashwant Kumar Balivada
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Mustafa Sameer
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sanchita ghosh
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The design of an FPGA based portable seizure detection system for epilepsy patients is presented in this paper. For complete hardware support, an FPGA based epilepsy detection system exploiting Artificial Neural Network (ANN) based classifier with on chip training and testing support have been presented in this paper. With the help of such Neural Network processor, the prevailing problems in software like latency can be overcome and, also one can proceed towards an ASIC design of such system which is in high demand in recent days in the field of neuromorphic computing. The proposed hardware design takes the epileptic seizure characteristics namely—mean, variance, skewness, and, kurtosis as the input vectors to the ANN model and generates the classification output similar to traditional software system but now with complete and isolated hardware support. The total framework which incorporates both training and testing has been designed using Verilog HDL on Xilinx Vivado software. The objective development board chosen for epileptic seizure detection implementation and testing was Xilinx Zedboard. The various seizure groups namely— (SZ, SO, SN, SF, S-ZO, S-NF, ZO-NF, S-ZONF) which are taken from 4 unique frequency based groups which are Alpha, Beta, Delta, Theta accomplishing an accuracy ranging from 70% to 90% for different models. Previously, hardware support had already been presented through software hardware co-design approach, where software based training were accompanied by hardware based testing on FPGA. But, the problem with this approach is that it needs repetitive tuning of weights on software to learn patterns on different datasets and then have to store it on hardware for testing/inference work. So, we troubleshooted this problem by our novel work where our proposed FPGA ANN architecture lessens this intricacy incredibly as hardware can train and test on FPGA itself without the need of external software assistance.