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Exploring Instruction Set Architectural Variations: x86, ARM, and RISC-V in Compute-Intensive Applications
  • Wajid Ali
Wajid Ali
University of Engineering and Technology Lahore

Corresponding Author:[email protected]

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Abstract

As computational demands continue to evolve in  the modern era, the choice of hardware architecture plays a  pivotal role in optimizing the performance of compute-intensive  applications. This research paper delves into the exploration  and comparison of three prominent hardware architectures:  x86, ARM, and RISC-V, within the context of compute-intensive  applications. The study begins with a comprehensive overview  of these architectures, highlighting their distinctive features,  and strengths. Subsequently, we investigate their suitability and  adaptability in diverse compute-intensive workloads. Our  analysis encompasses a wide spectrum of parameters, including  computational throughput, power efficiency, scalability, and  architectural flexibility. We scrutinize the architectural  intricacies that impact the execution of compute-intensive tasks,  shedding light on both the advantages and limitations of each  architecture. We used the gem5 simulator to compare these  Instruction Set Architectures (ISA). We run different  benchmarks on gem5 with different ISA and different  configurations and compare the result. Based on these results  we predict which architecture is better in which scenario. Gem5  is not a cycle accurate simulator but it’s a model accurate. In  conclusion, “Exploring Architectural Variations: x86, ARM,  and RISC-V in Compute-Intensive Applications” offers a  comprehensive insight into the nuances of hardware selection  for compute-intensive workloads. Our findings aid system  architects, researchers, and technology enthusiasts in making  informed decisions about the most suitable architectural choice  for their specific compute-intensive applications, ultimately  contributing to advancements in computational performance  and efficiency