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Wafer-level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes
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  • Samuel Parent ,
  • Frédéric Vachon ,
  • Valérie Gauthier ,
  • Steve Lamoureux ,
  • Alexandre Paquette ,
  • Jacob Deschamps ,
  • Tommy Rossignol ,
  • Nicolas Roy ,
  • Philippe Arsenault ,
  • Henri Dautet ,
  • Serge Charlebois ,
  • Jean-François Pratte
Samuel Parent
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Frédéric Vachon
Université de Sherbrooke

Corresponding Author:[email protected]

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Valérie Gauthier
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Steve Lamoureux
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Alexandre Paquette
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Jacob Deschamps
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Tommy Rossignol
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Nicolas Roy
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Philippe Arsenault
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Henri Dautet
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Serge Charlebois
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Jean-François Pratte
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When developing a technology based on single-photon avalanche diodes (SPADs), the SPAD characterization is mandatory to debug, optimize and monitor the microfabrication process. This is especially true for the development of SPAD arrays 3D integrated with CMOS readout electronics, where SPAD testing is required to qualify the process, independently from the final CMOS readout circuit. This work reports on a characterization and monitoring platform dedicated to SPAD testing at die and wafer level, in the context of a 3D SPAD technology development. The platform relies on a dedicated integrated circuit made in a standard CMOS technology and used in different configurations from a prototype printed circuit board (die-level testing) to active probe cards (wafer-level mapping). The platform gives full access to SPAD characteristics in Geiger mode such as the dark noise, photon detection efficiency and timing resolution. The integrated circuit and its configuration are described in detail as well as results obtained on different SPAD test structures. In particular, the dark count rate mapping demonstrates the benefits of testing SPADs at wafer level at the R&D stage.