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Novel RS-HS Algorithm Based Massive Throughput LDPC Decoder with Efficient Circuit Utilization
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  • Bhavya Shah ,
  • Prateek Mukherjee ,
  • Gaurav Purohit ,
  • C K ramesha ,
  • V. K. Choubey
Bhavya Shah

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Prateek Mukherjee
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Gaurav Purohit
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C K ramesha
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V. K. Choubey
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Low-density parity check codes (LDPC) are efficient in terms of coding performance and parallelism but need a higher code length to reduce the decoding complexity. In modern5G networks, hardware utilization issues have been addressed with a min-sum algorithm adopting quasi-cyclic LDPC. The present paper proposes a modified layered min-sum algorithm by presenting an intelligent strategy to introduce concurrency in processing by grouping the rows in the base matrix. The algorithm also considers the case where the column weight of a layer is greater than one and makes a suitable connection hierarchy to maximize hardware re-usability. The architecture employs the tree-structure (TS) approach to design an effective hardware block for the check-node unit (CNU). The proposed CNU architecture processes input belief parallelly and enhances hardware reusability by adapting data path reconfiguration. This scheme ensures that even though the processing of the grouped rows in the layer happens simultaneously, the rows are isolated from each other during this process. The routing and processing hardware architecture of the proposed system has been synthesized on Zinc-ultra scale+ zcu106 after functional verification on Xilinx-Vivado to claim an increase in throughput.