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Time Division Multiplexing for 1-bit Bandpass Delta-Sigma Modulator
  • Takashi Maehata,
  • Noriharu Suematsu
Takashi Maehata

Corresponding Author:[email protected]

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Noriharu Suematsu

Abstract

The 1-bit band-pass delta-sigma modulator (BP-DSM) achieves high resolution by using the oversampling technology. It can output a radio frequency signal directly from the digital components without using an analog frequency converter and local oscillator, thereby enabling a reduction in the size of the wireless equipment. On the other hand, this modulator itself is intrinsically difficult to reduce in size while increasing speed by time division multiplexing and parallel processing, because the modulator is composed of a feedback loop and forms a double feedback loop when the loop filter is used as an infinite impulse response filter. This paper introduces a noise transfer function NTF(z M) applying multiplicity M, and shows that time division multiplexing can be realized with a constant circuit size (number of multipliers and adders) and only additional memory. In addition, by distributing the additional memory, it is demonstrated that the critical path can be divided and the processing speed can be doubled from 114 MHz to 239 MHz, by designing an FPGA when M is two (two times multiplexing). Furthermore, it is demonstrated that the proposed modulator can perform concurrent multi-band transmission processing and/or MIMO system by multiplexing a 1-bit BP-DSM.
14 May 2024Submitted to TechRxiv
20 May 2024Published in TechRxiv