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Optimizing Wide Synchronous Up-Counters for FPGA Performance
  • David Castells-Rufas
David Castells-Rufas

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A binary up counter is presented, benefiting from the lower frequency characteristics of the higher-order bits to achieve high performance. The sequential circuit design is divided into two segments: a higher segment based on a slow counter design and a lower high-performance segment. The predictability and periodicity of directional counters is exploited to reduce the length of combinational paths to a minimum. This solution holds broad applicability for both ASIC and FPGA technologies. The design has been synthesized for two FPGA families: Intel Cyclone V and AMD UltraScale+. Comparative analysis against counter IP cores from Intel and AMD reveals that the proposed design consistently shows superior frequencies achieving up to a factor of 2.5× higher clock frequency having a resource consumption of approximately a factor 2× .
12 Jan 2024Submitted to TechRxiv
25 Jan 2024Published in TechRxiv