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Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme
  • +4
  • Marco Angioli,
  • Marcello Barbirotta,
  • Abdallah Cheikh,
  • Antonio Mastrandrea,
  • Francesco Menichelli,
  • Saeid Jamili,
  • Mauro Olivieri
Marco Angioli

Corresponding Author:[email protected]

Author Profile
Marcello Barbirotta
Abdallah Cheikh
Antonio Mastrandrea
Francesco Menichelli
Saeid Jamili
Mauro Olivieri


Integer division is key for various applications and often represents the performance bottleneck due to its inherent mathematical properties that limit its parallelization. This work proposes four 32bit data-dependent-latency division schemes, derived from the classic non-performing restoring division algorithm. The proposed technique exploits the relationship between the number of leading zeros in the divisor and in the partial remainder to dynamically detect and skip those iterations that result in a simple left shift. While a similar principle has been exploited in previous works, the proposed approach outperforms existing variable latency divider schemes in average latency and power consumption. We detail the algorithm and its implementation in four variants, offering versatility for the specific application requirements. For each variant, we report the average latency evaluated with different benchmarks, and then we analyze the synthesis results for both FPGA and ASIC deployment, reporting clock speed, average execution time, hardware resources, and energy consumption, compared with existing fixed and variable latency dividers.
23 Feb 2024Submitted to TechRxiv
27 Feb 2024Published in TechRxiv