loading page

Low Power and High-Speed Multi-Threshold CMOS-Data Flip-Flop Design Validation on 90nm Technology Node Using EDA Tools
  • +2
  • Bapuji Banothu,
  • Prahas Surabhi,
  • Bommidi Sridhar,
  • Ashangari Rakesh,
  • Chettipally Venu
Bapuji Banothu
UG Scholar, Dept of ECE, Scient Institute of technology

Corresponding Author:[email protected]

Author Profile
Prahas Surabhi
UG Scholar, Dept of ECE, Scient Institute of technology
Bommidi Sridhar
Dept of ECE, Scient Institute of technology
Ashangari Rakesh
Dept of ECE, Scient Institute of technology
Chettipally Venu
UG Scholar, Dept of ECE, Scient Institute of technology

Abstract

The primary focus of Research VLSI Technology is to optimize power and Delay, so that a low power and High Speed Designs are obtained. The MTCMOS is one of the Such Promising CMOS Chip technology that uses transistors with multiple threshold voltages to optimize power and Delay. Subthreshold Leakage has brought down and achieved power optimization. In this article Multi threshold CMOS based Data Flip-Flop is Designed, analyzed and Validated on 90 nm Technology Node Using EDA Tools.
16 May 2024Submitted to TechRxiv
21 May 2024Published in TechRxiv