Abstract
A single-event transient (SET) tolerant dynamic bias comparator
leveraging path-splitting is presented in this paper. The dynamic bias
structure with a tail capacitor is found to be vulnerable to positive
and negative SET transients. A negative transient on the tail transistor
doubles the energy per conversion. A positive transient on the tail MOS
capacitor reduces the preamplifier gain by 35.7%, which increases the
metastability error rate in the subsequent latch. A path splitting
technique is applied to mitigate the positive SET. Simulations in a
65-nm CMOS process showed that a two path split can recover the
comparator output voltage swing by 12.7%. Compared with the
state-of-the-art CMOS radiation-hardened by design (RHBD) dynamic
comparators, this circuit achieved the lowest energy per comparison
while maintaining low input referred noise and gaining SET tolerance in
the evaluation phase.