Abstract
This work explains the process of designing and synthesizing a MOD 13
binary down counter using 180 nm CMOS technology transistors. The
beginning of the count is a combination of 1110(2), the end of the count
is 0010(2). Simulations are made at the circuit level (transient
analysis) to verify that the circuit functions correctly, then the
integrated circuit layout is prepared by connecting the components
manually. Finally, the layout is simulated to see how the existence of
parasitic resistances and capacitances affect the output signals and it
is used to estimate the maximum allowable clock frequency (fclk).