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Design and Synthesis of a MOD 13 Down Counter.pdf (2.05 MB)
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Design and Synthesis of a MOD 13 Binary Down Counter

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posted on 19.10.2021, 13:31 authored by Ara Abdulsatar AssimAra Abdulsatar Assim
This work explains the process of designing and synthesizing a MOD 13 binary down counter using 180 nm CMOS technology transistors. The beginning of the count is a combination of 1110(2), the end of the count is 0010(2). Simulations are made at the circuit level (transient analysis) to verify that the circuit functions correctly, then the integrated circuit layout is prepared by connecting the components manually. Finally, the layout is simulated to see how the existence of parasitic resistances and capacitances affect the output signals and it is used to estimate the maximum allowable clock frequency (fclk).

History

Email Address of Submitting Author

araabdulsattar@gmail.com

ORCID of Submitting Author

https://orcid.org/0000-0002-6055-9223

Submitting Author's Institution

Peter the Great St. Petersburg Polytechnic University

Submitting Author's Country

Russian Federation